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| author | André Zwing <nerv@dawncrow.de> | 2025-05-12 18:28:38 +0200 |
|---|---|---|
| committer | André Zwing <nerv@dawncrow.de> | 2025-05-19 23:46:29 +0200 |
| commit | e07ec82344dd8d87c1a246bb9cfb4d74b8450842 (patch) | |
| tree | addcceac09adafe4d92980dcbc753c23f4be0627 /src/dynarec | |
| parent | 37eb5492ba5d58672620d77e01b1bd497cce00d9 (diff) | |
| download | box64-e07ec82344dd8d87c1a246bb9cfb4d74b8450842.tar.gz box64-e07ec82344dd8d87c1a246bb9cfb4d74b8450842.zip | |
[WOW64] Implement BTCpuSimulate
Diffstat (limited to 'src/dynarec')
| -rw-r--r-- | src/dynarec/arm64/arm64_epilog.S | 3 | ||||
| -rw-r--r-- | src/dynarec/arm64/arm64_next.S | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/dynarec/arm64/arm64_epilog.S b/src/dynarec/arm64/arm64_epilog.S index 57f23200..4a15895b 100644 --- a/src/dynarec/arm64/arm64_epilog.S +++ b/src/dynarec/arm64/arm64_epilog.S @@ -19,6 +19,9 @@ arm64_epilog: stp x24, x25, [x0, (8 * 14)] stp x26, x27, [x0, (8 * 16)] // put back reg value in emu, including EIP (so x27 must be EIP now) //restore all used register +#ifdef _WIN32 + ldr x18, [x0, 3120] +#endif add sp, x28, 0 //vpop {d8-d15} ldp x19, x20, [sp, (8 * 0)] diff --git a/src/dynarec/arm64/arm64_next.S b/src/dynarec/arm64/arm64_next.S index e900fbec..950b7dd3 100644 --- a/src/dynarec/arm64/arm64_next.S +++ b/src/dynarec/arm64/arm64_next.S @@ -22,6 +22,9 @@ arm64_next: stp x16, x17, [sp, (8 * 8)] stp x18, x27, [sp, (8 * 10)] // also save x27(rip) to allow change in LinkNext +#ifdef _WIN32 + ldr x18, [x0, 3120] +#endif mov x2, x30 // "from" is in lr, so put in x2 add x3, sp, 8*11 // x3 is address to change rip // call the function |