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| author | ptitSeb <seebastien.chev@gmail.com> | 2023-08-11 16:57:46 +0200 |
|---|---|---|
| committer | ptitSeb <seebastien.chev@gmail.com> | 2023-08-11 16:57:46 +0200 |
| commit | e8972efca192e988cdd72fc765ef001defe9a5a4 (patch) | |
| tree | 7cb6e0266e5c17740269c146223326b39b14accf /src/dynarec | |
| parent | f86c856e3ba53a0741d7d5f97f60c1a785547fe7 (diff) | |
| download | box64-e8972efca192e988cdd72fc765ef001defe9a5a4.tar.gz box64-e8972efca192e988cdd72fc765ef001defe9a5a4.zip | |
[32bits] Added 62 opcode ([ARM64_DYNAREC] too)
Diffstat (limited to 'src/dynarec')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_00.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c index 7bf9511f..df3f3d91 100644 --- a/src/dynarec/arm64/dynarec_arm64_00.c +++ b/src/dynarec/arm64/dynarec_arm64_00.c @@ -679,7 +679,16 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin DEFAULT; } break; - + case 0x62: + if(rex.is32bits) { + // BOUND here + DEFAULT; + } else { + INST_NAME("BOUND Gd, Ed"); + nextop = F8; + FAKEED(0); + } + break; case 0x63: if(rex.is32bits) { // ARPL here |