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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-07-08 12:43:44 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-07-08 12:43:44 +0200 |
| commit | fe6304b7cd752fbd8abd6d7aa86aeeb6ac8b9b66 (patch) | |
| tree | 9dc5da752657e20352b5e979299550316dd55066 /src/dynarec | |
| parent | e9b6f3559b49feea5ab058958f5b8c8c10ef3b81 (diff) | |
| download | box64-fe6304b7cd752fbd8abd6d7aa86aeeb6ac8b9b66.tar.gz box64-fe6304b7cd752fbd8abd6d7aa86aeeb6ac8b9b66.zip | |
[DYNAREC] Added 66 0F D2 opcodes (for geekbench5)
Diffstat (limited to 'src/dynarec')
| -rwxr-xr-x | src/dynarec/dynarec_arm64_660f.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c index bda5fdec..61afa927 100755 --- a/src/dynarec/dynarec_arm64_660f.c +++ b/src/dynarec/dynarec_arm64_660f.c @@ -1345,6 +1345,18 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n break; + case 0xD2: + INST_NAME("PSRLD Gx,Ex"); + nextop = F8; + GETGX(q0); + GETEX(q1, 0); + v0 = fpu_get_scratch(dyn); + SQSHRN_32(v0, q1, 0); // S64x1->S32x1 + VMOVeS(v0, 1, v0, 0); // S32x1->S32x2 + NEG_32(v0, v0); // neg, because SHR + VMOVeD(v0, 1, v0, 0); // S32x2->S32x4 + USHLQ_32(q0, q0, v0); // SHR x4 + break; case 0xD3: INST_NAME("PSRLQ Gx,Ex"); nextop = F8; |