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| author | ptitSeb <sebastien.chev@gmail.com> | 2024-02-23 16:41:44 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2024-02-23 16:41:44 +0100 |
| commit | ffda782c3d88d977acc12a3c2c2738719f9304ed (patch) | |
| tree | a0e1893fb28090c4f0f2a26c7a67bb40ae71f6b5 /src/dynarec | |
| parent | 3a6df996dc85257a5496ecb28a72579df225a176 (diff) | |
| download | box64-ffda782c3d88d977acc12a3c2c2738719f9304ed.tar.gz box64-ffda782c3d88d977acc12a3c2c2738719f9304ed.zip | |
Better handling of Hardware counter for rdtsc emulation (ARM64 only for now), more cpuid leafs, and introduce BOX64_RDTSC env.var. with a profile that use it
Diffstat (limited to 'src/dynarec')
| -rw-r--r-- | src/dynarec/arm64/arm64_emitter.h | 2 | ||||
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_0f.c | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h index d44fa5d9..7450fdd4 100644 --- a/src/dynarec/arm64/arm64_emitter.h +++ b/src/dynarec/arm64/arm64_emitter.h @@ -769,6 +769,8 @@ #define MSR_fpsr(Rt) EMIT(MRS_gen(0, 1, 3, 4, 4, 1, Rt)) // mrs x0, cntvct_el0 op0=0b11 op1=0b011 CRn=0b1110 CRm=0b0000 op2=0b010 #define MRS_cntvct_el0(Rt) EMIT(MRS_gen(1, 1, 0b011, 0b1110, 0b0000, 0b010, Rt)) +// mrs x0, cntpctss_el0 op0=0b11 op1=0b011 CRn=0b1110 CRm=0b0000 op2=0b101 +#define MRS_cntpctss_el0(Rt) EMIT(MRS_gen(1, 1, 0b011, 0b1110, 0b0000, 0b101, Rt)) // NEON Saturation Bit #define FPSR_QC 27 // NEON Input Denormal Cumulative diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index a19961bd..309f9622 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -482,7 +482,11 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin case 0x31: INST_NAME("RDTSC"); NOTEST(x1); - MRS_cntvct_el0(x1); + if(box64_rdtsc) { + CALL_(ReadTSC, x1, x3); + } else { + MRS_cntvct_el0(x1); + } LSRx(xRDX, x1, 32); MOVw_REG(xRAX, x1); // wipe upper part break; |