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| author | xctan <xctan@cirno.icu> | 2024-11-24 23:57:34 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-24 16:57:34 +0100 |
| commit | 3bde222242709abe778702b48c054a774c24c64a (patch) | |
| tree | 744cdf4c8deabdd31f4d3e3c94d7cc87771651f7 /src/include | |
| parent | d0af86d5bf670fd09b99e1c5058c825dfd182118 (diff) | |
| download | box64-3bde222242709abe778702b48c054a774c24c64a.tar.gz box64-3bde222242709abe778702b48c054a774c24c64a.zip | |
[RV64_DYNAREC] Added, fixed, and optimized opcodes (#2059)
* [RV64_DYNAREC] Added 66 0F 38 37 PCMPGTQ opcode * [RV64_DYNAREC] Added 66 0F 17 MOVHPD opcode * [RV64_DYNAREC] Added 66 0F 38 15 PBLENDVPD opcode * [RV64_DYNAREC] Optimized vector SSE packed compare * [RV64_DYNAREC] Optimized vector MMX MOVD Gm, Ed * [RV64_DYNAREC] Optimized vector SSE PMADDWD opcode * [RV64_DYNAREC] Added vector PCMPGTQ opcode * [RV64_DYNAREC] Added vector 66 0F 17 MOVHPD opcode * [RV64_DYNAREC] Optimized vector 66 0F 16 MOVHPD opcode * [RV64_DYNAREC] Added vector PBLENDVPD opcode * [RV64_DYNAREC] Optimized vector PMADDUBSW opcode * [RV64_DYNAREC] Optimized vector SSE logical shifts with Ex * [RV64_DYNAREC] Optimized vector SSE unpack * [RV64_DYNAREC] Added F0 F6 /2 LOCK NOT opcode * [RV64_DYNAREC] Fixed vector packed logical shift
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions