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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2023-03-24 20:12:42 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-24 13:12:42 +0100 |
| commit | 45015d6106133b940cbb5f24e08aac4d70bd7de8 (patch) | |
| tree | 712b816d0bf866fa6ae61db4048c9a30242ec16b /src/include | |
| parent | c3223245e561f1f78c4e2b053c43a14929df615e (diff) | |
| download | box64-45015d6106133b940cbb5f24e08aac4d70bd7de8.tar.gz box64-45015d6106133b940cbb5f24e08aac4d70bd7de8.zip | |
[RV64_DYNAREC] Added more opcodes & some fixes & some optimizations (#632)
* [RV64_DYNAREC] Added 66 D1,D3 SAR opcode * [RV64_DYNAREC] Added 66 F7 /7 IDIV opcode * [RV64_DYNAREC] Fixed 32 XOR opcode * [RV64_DYNAREC] Some small optims * [RV64_DYNAREC] Added 66 33 XOR opcode * [RV64_DYNAREC] Added 66 81,83 /6 XOR opcode * [RV64_DYNAREC] Added 66 31 XOR opcode * [RV64_DYNAREC] Fixed a typo in IDIV opcode * [RV64_DYNAREC] Added A4 REP MOVSB opcode * [RV64_DYNAREC] Fixed 66 35 XOR opcode * [RV64_DYNAREC] Added 66 39 CMP opcode * [RV64_DYNAREC] Added F6 /7 IDIV opcode * [RV64_DYNAREC] Added 1C SBB opcode * [RV64_DYNAREC] Added 66 05 ADD opcode
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions