diff options
| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-12-23 15:25:29 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-23 08:25:29 +0100 |
| commit | 0c7cc657cc3ef0b11330f51e96ca851393acbcec (patch) | |
| tree | 7e84fde62784aea5764a20f78def9ad2eca35adb /src | |
| parent | ce4590f5ba8c3a30e61c1d2be786258b6ad5da6c (diff) | |
| download | box64-0c7cc657cc3ef0b11330f51e96ca851393acbcec.tar.gz box64-0c7cc657cc3ef0b11330f51e96ca851393acbcec.zip | |
[LA64_DYNAREC] Fixed 32bit ADDIz and SUBz (#2191)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/la64/la64_emitter.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h index 86cf334b..70e28922 100644 --- a/src/dynarec/la64/la64_emitter.h +++ b/src/dynarec/la64/la64_emitter.h @@ -2069,9 +2069,10 @@ LSX instruction starts with V, LASX instruction starts with XV. #define ADDIz(rd, rj, imm12) \ do { \ - if (rex.is32bits) \ + if (rex.is32bits) { \ ADDI_W(rd, rj, imm12); \ - else \ + ZEROUP(rd); \ + } else \ ADDI_D(rd, rj, imm12); \ } while (0) @@ -2164,9 +2165,10 @@ LSX instruction starts with V, LASX instruction starts with XV. #define SUBz(rd, rj, rk) \ do { \ - if (rex.is32bits) \ + if (rex.is32bits) { \ SUB_W(rd, rj, rk); \ - else \ + ZEROUP(rd); \ + } else \ SUB_D(rd, rj, rk); \ } while (0) |