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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-31 10:08:09 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-31 10:08:09 +0200 |
| commit | 0d2a060e663b092b7c966a2a720b380f21e0a38f (patch) | |
| tree | 90c1ade3f570bf44feb75c08b309ab28943c99d7 /src | |
| parent | 9748c55dd025d6e6cc018c61a85b921b5a2e0fb3 (diff) | |
| download | box64-0d2a060e663b092b7c966a2a720b380f21e0a38f.tar.gz box64-0d2a060e663b092b7c966a2a720b380f21e0a38f.zip | |
[DYNAREC] Added F3 0F 2D opcode
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/dynarec_arm64_f30f.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c index c4b698b6..a46f6bad 100755 --- a/src/dynarec/dynarec_arm64_f30f.c +++ b/src/dynarec/dynarec_arm64_f30f.c @@ -138,7 +138,31 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n GETEX(d0, 0); FCVTZSxwS(gd, d0); break; - + case 0x2D: + INST_NAME("CVTSS2SI Gd, Ex"); + nextop = F8; + GETGD; + GETEX(q0, 0); + #ifdef PRECISE_CVT + LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr)); + UBFXx(x1, x1, 13, 2); // extract round requested + LSLx_REG(x1, x1, 3); + ADDx_U12(x1, x1, 8); // add the actual add+jump opcodes + // Construct a "switch case", with each case 2 instructions, so 8 bytes + BL(+4); // Branch with Link to next, so LR gets next PC address + ADDx_REG(xLR, xLR, x1); + B(xLR); // could use RET, but it's not really one + FCVTNSxwS(gd, q0); // 0: Nearest (even) + B_NEXT_nocond; + FCVTMSxwS(gd, q0); // 1: Toward -inf + B_NEXT_nocond; + FCVTPSxwS(gd, q0); // 2: Toward +inf + B_NEXT_nocond; + FCVTZSxwS(gd, q0); // 3: Toward 0 + #else + FCVTNSxwS(gd, q0); + #endif + break; case 0x51: INST_NAME("SQRTSS Gx, Ex"); nextop = F8; |