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authorptitSeb <sebastien.chev@gmail.com>2021-04-01 13:23:17 +0200
committerptitSeb <sebastien.chev@gmail.com>2021-04-01 13:23:17 +0200
commit1c3f4c078f982d0531ee0e4201baf0e1aea8d96a (patch)
tree924843410cbae45df3ec0acc4ca8e8dcf9327621 /src
parent48588a25568577aca862c1a11fcbc713e63cf523 (diff)
downloadbox64-1c3f4c078f982d0531ee0e4201baf0e1aea8d96a.tar.gz
box64-1c3f4c078f982d0531ee0e4201baf0e1aea8d96a.zip
Added 66 0F 3A 0F opcode ([DYNAREC] too)
Diffstat (limited to 'src')
-rwxr-xr-xsrc/dynarec/dynarec_arm64_660f.c24
-rw-r--r--src/emu/x64run660f.c24
2 files changed, 48 insertions, 0 deletions
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index 72c81902..006848d6 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -258,6 +258,30 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             }

             break;

 

+        case 0x3A:  // these are some more SSSE3 opcodes

+            opcode = F8;

+            switch(opcode) {

+                case 0x0F:

+                    INST_NAME("PALIGNR Gx, Ex, Ib");

+                    nextop = F8;

+                    GETGX(q0);

+                    GETEX(q1, 1);

+                    u8 = F8;

+                    if(u8>31) {

+                        VEORQ(q0, q0, q0);    

+                    } else if(u8>15) {

+                        d0 = fpu_get_scratch(dyn);

+                        VEORQ(d0, d0, d0);

+                        VEXTQ_8(q0, q0, d0, u8-16);

+                    } else {

+                        VEXTQ_8(q0, q1, q0, u8);

+                    }

+                    break;

+                default:

+                    DEFAULT;

+            }

+            break;

+

         #define GO(GETFLAGS, NO, YES, F)            \

             READFLAGS(F);                           \

             GETFLAGS;                               \

diff --git a/src/emu/x64run660f.c b/src/emu/x64run660f.c
index be2e8d9b..f18e8874 100644
--- a/src/emu/x64run660f.c
+++ b/src/emu/x64run660f.c
@@ -253,6 +253,30 @@ int Run660F(x64emu_t *emu, rex_t rex)
         }

         break;

 

+    case 0x3A:  // these are some SSE3 opcodes

+        opcode = F8;

+        switch(opcode) {

+            case 0x0F:          // PALIGNR GX, EX, u8

+                nextop = F8;

+                GETEX(1);

+                GETGX;

+                tmp8u = F8;

+                if(tmp8u>31)

+                    {GX->q[0] = GX->q[1] = 0;}

+                else

+                {

+                    for (int i=0; i<16; ++i, ++tmp8u)

+                        eax1.ub[i] = (tmp8u>15)?((tmp8u>31)?0:GX->ub[tmp8u-16]):EX->ub[tmp8u];

+                    GX->q[0] = eax1.q[0];

+                    GX->q[1] = eax1.q[1];

+                }

+                break;

+

+            default:

+                return 1;

+        }

+        break;

+        

     GOCOND(0x40

         , nextop = F8;

         CHECK_FLAGS(emu);