[LA64_DYNAREC] Added more LBT instructions to the printer (#1356)

2 files changed, 168 insertions, 28 deletions

diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h
index 1d1968f2..c46d5512 100644
--- a/src/dynarec/la64/la64_emitter.h
+++ b/src/dynarec/la64/la64_emitter.h
@@ -658,34 +658,34 @@ f24-f31  fs0-fs7   Static registers                Callee
 #define X64_XOR_H(rj, rk)   EMIT(type_3R(0x7f, rk, rj, 0x19))
 #define X64_XOR_W(rj, rk)   EMIT(type_3R(0x7f, rk, rj, 0x1a))
 #define X64_XOR_D(rj, rk)   EMIT(type_3R(0x7f, rk, rj, 0x1b))
-#define X64SLLI_B(rj, imm3)     EMIT(type_2RI3(0x2a1, imm3, rj, 0x0))
-#define X64SRLI_B(rj, imm3)     EMIT(type_2RI3(0x2a1, imm3, rj, 0x4))
-#define X64SRAI_B(rj, imm3)     EMIT(type_2RI3(0x2a1, imm3, rj, 0x8))
-#define X64ROTRI_B(rj, imm3)    EMIT(type_2RI3(0x2a1, imm3, rj, 0xc))
-#define X64RCRI_B(rj, imm3)     EMIT(type_2RI3(0x2a1, imm3, rj, 0x10))
-#define X64ROTLI_B(rj, imm3)    EMIT(type_2RI3(0x2a1, imm3, rj, 0x14))
-#define X64RCLI_B(rj, imm3)     EMIT(type_2RI3(0x2a1, imm3, rj, 0x18))
-#define X64SLLI_H(rj, imm4)     EMIT(type_2RI4(0x151, imm4, rj, 0x1))
-#define X64SRLI_H(rj, imm4)     EMIT(type_2RI4(0x151, imm4, rj, 0x5))
-#define X64SRAI_H(rj, imm4)     EMIT(type_2RI4(0x151, imm4, rj, 0x9))
-#define X64ROTRI_H(rj, imm4)    EMIT(type_2RI4(0x151, imm4, rj, 0xd))
-#define X64RCRI_H(rj, imm4)     EMIT(type_2RI4(0x151, imm4, rj, 0x11))
-#define X64ROTLI_H(rj, imm4)    EMIT(type_2RI4(0x151, imm4, rj, 0x15))
-#define X64RCLI_H(rj, imm4)     EMIT(type_2RI4(0x151, imm4, rj, 0x19))
-#define X64SLLI_W(rj, imm5)     EMIT(type_2RI5(0xa9, imm5, rj, 0x2))
-#define X64SRLI_W(rj, imm5)     EMIT(type_2RI5(0xa9, imm5, rj, 0x6))
-#define X64SRAI_W(rj, imm5)     EMIT(type_2RI5(0xa9, imm5, rj, 0xa))
-#define X64ROTRI_W(rj, imm5)    EMIT(type_2RI5(0xa9, imm5, rj, 0xe))
-#define X64RCRI_W(rj, imm5)     EMIT(type_2RI5(0xa9, imm5, rj, 0x12))
-#define X64ROTLI_W(rj, imm5)    EMIT(type_2RI5(0xa9, imm5, rj, 0x16))
-#define X64RCLI_W(rj, imm5)     EMIT(type_2RI5(0xa9, imm5, rj, 0x1a))
-#define X64SLLI_D(rj, imm6)     EMIT(type_2RI6(0x55, imm6, rj, 0x3))
-#define X64SRLI_D(rj, imm6)     EMIT(type_2RI6(0x55, imm6, rj, 0x7))
-#define X64SRAI_D(rj, imm6)     EMIT(type_2RI6(0x55, imm6, rj, 0xb))
-#define X64ROTRI_D(rj, imm6)    EMIT(type_2RI6(0x55, imm6, rj, 0xf))
-#define X64RCRI_D(rj, imm6)     EMIT(type_2RI6(0x55, imm6, rj, 0x13))
-#define X64ROTLI_D(rj, imm6)    EMIT(type_2RI6(0x55, imm6, rj, 0x17))
-#define X64RCLI_D(rj, imm6)     EMIT(type_2RI6(0x55, imm6, rj, 0x1b))
+#define X64_SLLI_B(rj, imm3)    EMIT(type_2RI3(0x2a1, imm3, rj, 0x0))
+#define X64_SRLI_B(rj, imm3)    EMIT(type_2RI3(0x2a1, imm3, rj, 0x4))
+#define X64_SRAI_B(rj, imm3)    EMIT(type_2RI3(0x2a1, imm3, rj, 0x8))
+#define X64_ROTRI_B(rj, imm3)   EMIT(type_2RI3(0x2a1, imm3, rj, 0xc))
+#define X64_RCRI_B(rj, imm3)    EMIT(type_2RI3(0x2a1, imm3, rj, 0x10))
+#define X64_ROTLI_B(rj, imm3)   EMIT(type_2RI3(0x2a1, imm3, rj, 0x14))
+#define X64_RCLI_B(rj, imm3)    EMIT(type_2RI3(0x2a1, imm3, rj, 0x18))
+#define X64_SLLI_H(rj, imm4)    EMIT(type_2RI4(0x151, imm4, rj, 0x1))
+#define X64_SRLI_H(rj, imm4)    EMIT(type_2RI4(0x151, imm4, rj, 0x5))
+#define X64_SRAI_H(rj, imm4)    EMIT(type_2RI4(0x151, imm4, rj, 0x9))
+#define X64_ROTRI_H(rj, imm4)   EMIT(type_2RI4(0x151, imm4, rj, 0xd))
+#define X64_RCRI_H(rj, imm4)    EMIT(type_2RI4(0x151, imm4, rj, 0x11))
+#define X64_ROTLI_H(rj, imm4)   EMIT(type_2RI4(0x151, imm4, rj, 0x15))
+#define X64_RCLI_H(rj, imm4)    EMIT(type_2RI4(0x151, imm4, rj, 0x19))
+#define X64_SLLI_W(rj, imm5)    EMIT(type_2RI5(0xa9, imm5, rj, 0x2))
+#define X64_SRLI_W(rj, imm5)    EMIT(type_2RI5(0xa9, imm5, rj, 0x6))
+#define X64_SRAI_W(rj, imm5)    EMIT(type_2RI5(0xa9, imm5, rj, 0xa))
+#define X64_ROTRI_W(rj, imm5)   EMIT(type_2RI5(0xa9, imm5, rj, 0xe))
+#define X64_RCRI_W(rj, imm5)    EMIT(type_2RI5(0xa9, imm5, rj, 0x12))
+#define X64_ROTLI_W(rj, imm5)   EMIT(type_2RI5(0xa9, imm5, rj, 0x16))
+#define X64_RCLI_W(rj, imm5)    EMIT(type_2RI5(0xa9, imm5, rj, 0x1a))
+#define X64_SLLI_D(rj, imm6)    EMIT(type_2RI6(0x55, imm6, rj, 0x3))
+#define X64_SRLI_D(rj, imm6)    EMIT(type_2RI6(0x55, imm6, rj, 0x7))
+#define X64_SRAI_D(rj, imm6)    EMIT(type_2RI6(0x55, imm6, rj, 0xb))
+#define X64_ROTRI_D(rj, imm6)   EMIT(type_2RI6(0x55, imm6, rj, 0xf))
+#define X64_RCRI_D(rj, imm6)    EMIT(type_2RI6(0x55, imm6, rj, 0x13))
+#define X64_ROTLI_D(rj, imm6)   EMIT(type_2RI6(0x55, imm6, rj, 0x17))
+#define X64_RCLI_D(rj, imm6)    EMIT(type_2RI6(0x55, imm6, rj, 0x1b))
 
 ////////////////////////////////////////////////////////////////////////////////
 
diff --git a/src/dynarec/la64/la64_printer.c b/src/dynarec/la64/la64_printer.c
index bacecfb8..742d730b 100644
--- a/src/dynarec/la64/la64_printer.c
+++ b/src/dynarec/la64/la64_printer.c
@@ -885,6 +885,146 @@ const char* la64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "%-15s %s, %s", "X64XOR.D", Xt[Rj], Xt[Rk]);
         return buff;
     }
+    // X64SLLI.B
+    if(isMask(opcode, "0000000001010100001iiijjjjj00000", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SLLI.B", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRLI.B
+    if(isMask(opcode, "0000000001010100001iiijjjjj00100", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRLI.B", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRAI.B
+    if(isMask(opcode, "0000000001010100001iiijjjjj01000", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRAI.B", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTRI.B
+    if(isMask(opcode, "0000000001010100001iiijjjjj01100", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTRI.B", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCRI.B
+    if(isMask(opcode, "0000000001010100001iiijjjjj10000", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCRI.B", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTLI.B
+    if(isMask(opcode, "0000000001010100001iiijjjjj10100", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTLI.B", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCLI.B
+    if(isMask(opcode, "0000000001010100001iiijjjjj11000", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCLI.B", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SLLI.H
+    if(isMask(opcode, "000000000101010001iiiijjjjj00001", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SLLI.H", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRLI.H
+    if(isMask(opcode, "000000000101010001iiiijjjjj00101", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRLI.H", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRAI.H
+    if(isMask(opcode, "000000000101010001iiiijjjjj01001", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRAI.H", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTRI.H
+    if(isMask(opcode, "000000000101010001iiiijjjjj01101", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTRI.H", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCRI.H
+    if(isMask(opcode, "000000000101010001iiiijjjjj10001", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCRI.H", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTLI.H
+    if(isMask(opcode, "000000000101010001iiiijjjjj10101", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTLI.H", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCLI.H
+    if(isMask(opcode, "000000000101010001iiiijjjjj11001", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCLI.H", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SLLI.W
+    if(isMask(opcode, "00000000010101001iiiiijjjjj00010", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SLLI.W", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRLI.W
+    if(isMask(opcode, "00000000010101001iiiiijjjjj00110", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRLI.W", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRAI.W
+    if(isMask(opcode, "00000000010101001iiiiijjjjj01010", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRAI.W", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTRI.W
+    if(isMask(opcode, "00000000010101001iiiiijjjjj01110", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTRI.W", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCRI.W
+    if(isMask(opcode, "00000000010101001iiiiijjjjj10010", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCRI.W", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTLI.W
+    if(isMask(opcode, "00000000010101001iiiiijjjjj10110", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTLI.W", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCLI.W
+    if(isMask(opcode, "00000000010101001iiiiijjjjj11010", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCLI.W", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SLLI.D
+    if(isMask(opcode, "0000000001010101iiiiiijjjjj00011", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SLLI.D", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRLI.D
+    if(isMask(opcode, "0000000001010101iiiiiijjjjj00111", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRLI.D", Xt[Rj], imm);
+        return buff;
+    }
+    // X64SRAI.D
+    if(isMask(opcode, "0000000001010101iiiiiijjjjj01011", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64SRAI.D", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTRI.D
+    if(isMask(opcode, "0000000001010101iiiiiijjjjj01111", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTRI.D", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCRI.D
+    if(isMask(opcode, "0000000001010101iiiiiijjjjj10011", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCRI.D", Xt[Rj], imm);
+        return buff;
+    }
+    // X64ROTLI.D
+    if(isMask(opcode, "0000000001010101iiiiiijjjjj10111", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64ROTLI.D", Xt[Rj], imm);
+        return buff;
+    }
+    // X64RCLI.D
+    if(isMask(opcode, "0000000001010101iiiiiijjjjj11011", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %d", "X64RCLI.D", Xt[Rj], imm);
+        return buff;
+    }
 
     snprintf(buff, sizeof(buff), "%08X ???", __builtin_bswap32(opcode));
     return buff;