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| author | ptitSeb <sebastien.chev@gmail.com> | 2025-01-18 15:46:48 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2025-01-18 15:46:48 +0100 |
| commit | 1fe213f90056eb6567d4a3336c6063bff17ad62f (patch) | |
| tree | 102a108a49078c26612436f5d55adff235cf01cf /src | |
| parent | 802002b7a3d55d4810ac21e2fbbaaa6b35787296 (diff) | |
| download | box64-1fe213f90056eb6567d4a3336c6063bff17ad62f.tar.gz box64-1fe213f90056eb6567d4a3336c6063bff17ad62f.zip | |
[ARM64_DYNAREC] Fixed OF flags for rcr 8bits and 16bits
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_emit_shift.c | 29 |
1 files changed, 12 insertions, 17 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_emit_shift.c b/src/dynarec/arm64/dynarec_arm64_emit_shift.c index e6bac6eb..fa779a29 100644 --- a/src/dynarec/arm64/dynarec_arm64_emit_shift.c +++ b/src/dynarec/arm64/dynarec_arm64_emit_shift.c @@ -1083,7 +1083,12 @@ void emit_rcr8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s c%=9; IFX(X_OF) { - MOVw_REG(s3, wFlags); + if(c==1) { + EORw_REG_LSR(s3, xFlags, s1, 7); + BFIw(xFlags, s3, F_OF, 1); + } else if(box64_dynarec_test) { + BFCw(xFlags, F_OF, 1); + } } BFIw(s1, xFlags, 8, 1); // insert cf IFX(X_CF) { @@ -1093,14 +1098,6 @@ void emit_rcr8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s ORRw_REG_LSL(s1, s1, s1, 9); // insert s1 again } LSRw_IMM(s1, s1, c); // do the rcr - IFX(X_OF) { - if(c==1) { - EORw_REG_LSR(s3, s3, s1, 7); - BFIw(xFlags, s3, F_OF, 1); - } else if(box64_dynarec_test) { - BFCw(xFlags, F_OF, 1); - } - } } // emit RCL16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch @@ -1148,6 +1145,12 @@ void emit_rcr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int c%=17; BFIw(s1, xFlags, 16, 1); // insert cf IFX(X_OF) { + if(c==1) { + EORw_REG_LSR(s3, xFlags, s1, 15); + BFIw(xFlags, s3, F_OF, 1); + } else if(box64_dynarec_test) { + BFCw(xFlags, F_OF, 1); + } MOVw_REG(s3, wFlags); } IFX(X_CF) { @@ -1157,14 +1160,6 @@ void emit_rcr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int ORRx_REG_LSL(s1, s1, s1, 17); // insert s1 again } LSRx_IMM(s1, s1, c); // do the rcr - IFX(X_OF) { - if(c==1) { - EORw_REG_LSR(s3, s3, s1, 15); - BFIw(xFlags, s3, F_OF, 1); - } else if(box64_dynarec_test) { - BFCw(xFlags, F_OF, 1); - } - } } // emit RCL32/RCL64 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch |