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| author | ptitSeb <sebastien.chev@gmail.com> | 2024-05-22 23:51:54 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2024-05-22 23:51:54 +0200 |
| commit | 22b2f63917e0125567dd4a152c98a87ba27bd896 (patch) | |
| tree | 775a8bc2e04e5e1a512be30363c1637ae0ddb0dc /src | |
| parent | 5bcfa34bea51726cf066772af7b5100f6a1d08b4 (diff) | |
| download | box64-22b2f63917e0125567dd4a152c98a87ba27bd896.tar.gz box64-22b2f63917e0125567dd4a152c98a87ba27bd896.zip | |
[ARM64_DYNAREC] Small potential fix to D9 E5 opcode
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_d9.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_d9.c b/src/dynarec/arm64/dynarec_arm64_d9.c index 8e3107b2..6c99871d 100644 --- a/src/dynarec/arm64/dynarec_arm64_d9.c +++ b/src/dynarec/arm64/dynarec_arm64_d9.c @@ -165,6 +165,12 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } // load tag LDRH_U12(x3, xEmu, offsetof(x64emu_t, fpu_tags)); + if(i2<0) { + LSLw_IMM(x3, x3, -i2*2); + } else if(i2>0) { + ORRw_mask(x3, x3, 0b010000, 0b001111); // 0xffff0000 + LSRw_IMM(x3, x3, i2*2); + } TSTw_mask(x3, 0, 1); // 0b11 B_MARK3(cNE); // empty: C3,C2,C0 = 101 // load x2 with ST0 anyway, for sign extraction |