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| author | ptitSeb <sebastien.chev@gmail.com> | 2024-05-21 14:35:45 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2024-05-21 14:35:45 +0200 |
| commit | 24d1250e66996cddd4c813af55e7add860fa0e1b (patch) | |
| tree | f907fe9678ca8f7b16c205fb8bf48447af420bb3 /src | |
| parent | 706ca3649e830bd52529096092496e358ee53085 (diff) | |
| download | box64-24d1250e66996cddd4c813af55e7add860fa0e1b.tar.gz box64-24d1250e66996cddd4c813af55e7add860fa0e1b.zip | |
[ARM64_DYNAREC] Some small fixes to D9 E5 opcode
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_d9.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_d9.c b/src/dynarec/arm64/dynarec_arm64_d9.c index 5690e6be..8e3107b2 100644 --- a/src/dynarec/arm64/dynarec_arm64_d9.c +++ b/src/dynarec/arm64/dynarec_arm64_d9.c @@ -151,27 +151,24 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } } CMPSw_U12(x3, 0); - MOV32w(x3, 0b100000100000000); - CSELx(x4, x3, x4, cLE); // empty: C3,C2,C0 = 101 + MOV32w(x4, 0b100000100000000); // empty: C3,C2,C0 = 101 B_MARK3(cLE); - // x4 will be the actual top - LDRw_U12(x4, xEmu, offsetof(x64emu_t, top)); + // x5 will be the actual top + LDRw_U12(x5, xEmu, offsetof(x64emu_t, top)); if(i2) { if(i2<0) { - SUBw_U12(x4, x4, -i2); + SUBw_U12(x5, x5, -i2); } else { - ADDw_U12(x4, x4, i2); + ADDw_U12(x5, x5, i2); } - ANDw_mask(x4, x4, 0, 3); // (emu->top + i)&7 + ANDw_mask(x5, x5, 0, 3); // (emu->top + i)&7 } // load tag LDRH_U12(x3, xEmu, offsetof(x64emu_t, fpu_tags)); TSTw_mask(x3, 0, 1); // 0b11 - MOV32w(x3, 0b100000100000000); - CSELx(x4, x3, x4, cNE); // empty: C3,C2,C0 = 101 - B_MARK3(cNE); + B_MARK3(cNE); // empty: C3,C2,C0 = 101 // load x2 with ST0 anyway, for sign extraction - ADDx_REG_LSL(x1, xEmu, x4, 3); + ADDx_REG_LSL(x1, xEmu, x5, 3); LDRx_U12(x2, x1, offsetof(x64emu_t, x87)); } } else { @@ -183,8 +180,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin LSRx_IMM(x1, x2, 20+32); ANDSx_mask(x1, x1, 1, 0b00000, 0b001010); // 0x7ff B_MARK(cNE); // not zero or denormal - ANDx_mask(x1, x3, 1, 0, 0b111110); // 0x7fffffffffffffff - ORRx_REG(x1, x1, x2); + ANDSx_mask(x1, x2, 1, 0, 0b111110); // 0x7fffffffffffffff MOV32w(x4, 0b100000000000000); // Zero: C3,C2,C0 = 100 MOV32w(x5, 0b100010000000000); // Denormal: C3,C2,C0 = 110 CSELx(x4, x4, x5, cEQ); |