[ARM64_DYNAREC] More fixes for Atomics extension

4 files changed, 10 insertions, 13 deletions

diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h
index 9b6cc2e2..3f8105ef 100644
--- a/src/dynarec/arm64/arm64_emitter.h
+++ b/src/dynarec/arm64/arm64_emitter.h
@@ -2125,9 +2125,9 @@
 
 #define CASP_gen(size, L, Rs, O0, Rn, Rt)   ((size)<<30 | 0b001000<<24 | 0<<23 | (L)<<22 | 1<<21 | (Rs)<<16 | (O0)<<15 | 0b11111<<10 | (Rn)<<5 | (Rt))
 // Compare and Swap with pair, Rs, Rs+1 and Rt,Rt+1 with [Rt]
-#define CASPxw(Rs, Rt, Rn)              EMIT(CAS_gen(0b00+rex.w, 0, Rs, 0, Rn, Rt))
-#define CASPAxw(Rs, Rt, Rn)             EMIT(CAS_gen(0b00+rex.w, 1, Rs, 0, Rn, Rt))
-#define CASPALxw(Rs, Rt, Rn)            EMIT(CAS_gen(0b00+rex.w, 1, Rs, 1, Rn, Rt))
-#define CASPLxw(Rs, Rt, Rn)             EMIT(CAS_gen(0b00+rex.w, 0, Rs, 1, Rn, Rt))
+#define CASPxw(Rs, Rt, Rn)              EMIT(CASP_gen(0b00+rex.w, 0, Rs, 0, Rn, Rt))
+#define CASPAxw(Rs, Rt, Rn)             EMIT(CASP_gen(0b00+rex.w, 1, Rs, 0, Rn, Rt))
+#define CASPALxw(Rs, Rt, Rn)            EMIT(CASP_gen(0b00+rex.w, 1, Rs, 1, Rn, Rt))
+#define CASPLxw(Rs, Rt, Rn)             EMIT(CASP_gen(0b00+rex.w, 0, Rs, 1, Rn, Rt))
 
 #endif  //__ARM64_EMITTER_H__
diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c
index c42adeaf..f2c3cd60 100644
--- a/src/dynarec/arm64/dynarec_arm64_00.c
+++ b/src/dynarec/arm64/dynarec_arm64_00.c
@@ -1052,7 +1052,6 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 BFIx(gb1, x1, gb2, 8);
                 BFIx(eb1, x4, eb2, 8);
             } else {
-                SMDMB();
                 GETGB(x4);
                 addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
                 if(arm64_atomics) {
@@ -1064,7 +1063,6 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     // do the swap 4 -> strb(ed), 1 -> gd
                     STLXRB(x3, x4, ed);
                     CBNZx_MARKLOCK(x3);
-                    SMDMB();
                 }
                 BFIx(gb1, x1, gb2, 8);
             }
@@ -1081,7 +1079,6 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             } else {
                 GETGD;
                 addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
-                SMDMB();
                 TSTx_mask(ed, 1, 0, 1+rex.w);    // mask=3 or 7
                 B_MARK(cNE);
                 if(arm64_atomics) {
@@ -1095,13 +1092,14 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     B_MARK2_nocond;
                 }
                 MARK;
+                SMDMB();
                 LDRxw_U12(x1, ed, 0);
                 LDAXRB(x3, ed);
                 STLXRB(x3, gd, ed);
                 CBNZx_MARK(x3);
                 STRxw_U12(gd, ed, 0);
-                MARK2;
                 SMDMB();
+                MARK2;
                 MOVxw_REG(gd, x1);
             }
             break;
diff --git a/src/dynarec/arm64/dynarec_arm64_66f0.c b/src/dynarec/arm64/dynarec_arm64_66f0.c
index c5faa8da..df60a75f 100644
--- a/src/dynarec/arm64/dynarec_arm64_66f0.c
+++ b/src/dynarec/arm64/dynarec_arm64_66f0.c
@@ -87,7 +87,6 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                     SETFLAGS(X_ALL, SF_SET_PENDING);
                     nextop = F8;
                     GETGD;
-                    SMDMB();
                     UXTHw(x6, xRAX);
                     if(MODREG) {
                         ed = xRAX+(nextop&7)+(rex.b<<3);
@@ -102,7 +101,8 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                         B_MARK3(cNE);
                         // Aligned version
                         if(arm64_atomics) {
-                            CASALH(x6, x1, wback);
+                            MOVw_REG(x1, x6);
+                            CASALH(x1, gd, wback);
                         } else {
                             MARKLOCK;
                             LDAXRH(x1, wback);
@@ -124,12 +124,12 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                         STLXRB(x4, gd, wback);
                         CBNZx_MARK3(x4);
                         STRH_U12(gd, wback, 0);
+                        SMDMB();
                     }
                     MARK;
                     // Common part (and fallback for EAX != Ed)
                     UFLAG_IF {emit_cmp16(dyn, ninst, x6, x1, x3, x4, x5);}
                     BFIx(xRAX, x1, 0, 16);
-                    SMDMB();
                     break;
 
                 case 0xC1:
diff --git a/src/dynarec/arm64/dynarec_arm64_f0.c b/src/dynarec/arm64/dynarec_arm64_f0.c
index 08a54f59..f795cf92 100644
--- a/src/dynarec/arm64/dynarec_arm64_f0.c
+++ b/src/dynarec/arm64/dynarec_arm64_f0.c
@@ -474,7 +474,6 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                     CSETw(x2, cEQ);
                                     ANDw_REG(x1, x1, x2);
                                 }
-                                B_MARK3_nocond;
                             } else {
                                 MARKLOCK;
                                 LDAXPxw(x2, x3, wback);
@@ -545,7 +544,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             nextop = F8;
             GETGD;
             SMDMB();
-                if(MODREG) {
+            if(MODREG) {
                 ed = xRAX+(nextop&7)+(rex.b<<3);
                 emit_adc32(dyn, ninst, rex, ed, gd, x3, x4);
             } else {