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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-01-28 10:38:26 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-01-28 10:38:26 +0100 |
| commit | 282e242f5e5ac86176b3957b932e8feed88b7506 (patch) | |
| tree | 5b44a8daeef71d2ebc2e0c1aa328718321970745 /src | |
| parent | 13deb8d8d7b2e3f91f512cec16dde704091a08c8 (diff) | |
| download | box64-282e242f5e5ac86176b3957b932e8feed88b7506.tar.gz box64-282e242f5e5ac86176b3957b932e8feed88b7506.zip | |
[DYNAREC] Improved Strong Memory Model emulation
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/arm64/dynarec_arm64_helper.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h index dcffd85d..6e1d3a2d 100755 --- a/src/dynarec/arm64/dynarec_arm64_helper.h +++ b/src/dynarec/arm64/dynarec_arm64_helper.h @@ -36,9 +36,9 @@ // Sequence of Read will trigger a DMB on "first" read if strongmem is 2 // Squence of Write will trigger a DMB on "last" write if strongmem is 1 // Opcode will read -#define SMREAD() if(!dyn->smread && box64_dynarec_strongmem>1) {DMB_ISH(); dyn->smread=1;} +#define SMREAD() if(!dyn->smread && box64_dynarec_strongmem>1) {SMDMB();} // Opcode will read with option forced lock -#define SMREADLOCK(lock) if(lock) {SMDMB();} else if(!dyn->smread && box64_dynarec_strongmem>1) {DMB_ISH(); dyn->smread=1;} +#define SMREADLOCK(lock) if(lock || (!dyn->smread && box64_dynarec_strongmem>1)) {SMDMB();} // Opcode migh read (depend on nextop) #define SMMIGHTREAD() if(!MODREG) {SMREAD();} // Opcode has wrote @@ -54,7 +54,7 @@ // End of sequence #define SMEND() if(dyn->smwrite && box64_dynarec_strongmem) {DMB_ISH();} dyn->smwrite=0; dyn->smread=0; // Force a Data memory barrier (for LOCK: prefix) -#define SMDMB() DMB_ISH(); if(dyn->smwrite) dyn->smwrite=0; dyn->smread=1 +#define SMDMB() DMB_ISH(); dyn->smwrite=0; dyn->smread=1 //LOCK_* define #define LOCK_LOCK (int*)1 |