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authorptitSeb <sebastien.chev@gmail.com>2025-03-17 15:40:20 +0100
committerptitSeb <sebastien.chev@gmail.com>2025-03-17 15:40:20 +0100
commit3336cb6248193ff93b25c2a2ef932e2ecb0a4ddf (patch)
treef34dc3452e1b4105215de6b236272f8796ca4b4d /src
parent7fa3a1e627fe815b05751c223f4923e0d34addd1 (diff)
downloadbox64-3336cb6248193ff93b25c2a2ef932e2ecb0a4ddf.tar.gz
box64-3336cb6248193ff93b25c2a2ef932e2ecb0a4ddf.zip
[ARM64_DYNAREC] Small optim on special case of LOCK OR [RSP], 0
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_f0.c34
1 files changed, 19 insertions, 15 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_f0.c b/src/dynarec/arm64/dynarec_arm64_f0.c
index d65bc551..d5a81fef 100644
--- a/src/dynarec/arm64/dynarec_arm64_f0.c
+++ b/src/dynarec/arm64/dynarec_arm64_f0.c
@@ -375,7 +375,6 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                     // EAX == Ed
                                     STLXRxw(x4, gd, wback);
                                     CBNZx_MARKLOCK(x4);
-                                    SMDMB();
                                     // done
                                     if(!ALIGNED_ATOMICxw) {
                                         B_MARK_nocond;
@@ -394,9 +393,9 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                     STLXRB(x4, gd, wback);
                                     CBNZx_MARK3(x4);
                                     STRxw_U12(gd, wback, 0);
-                                    SMDMB();
                                 }
                                 MARK;
+                                SMDMB();
                                 // Common part (and fallback for EAX != Ed)
                                 UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, x1, x3, x4, x5); MOVxw_REG(xRAX, x1);}
                                 else {
@@ -1368,22 +1367,27 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     } else {
                         addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?4:1);
                         if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        if(arm64_atomics) {
-                            MOV64xw(x5, i64);
-                            UFLAG_IF {
-                                LDSETALxw(x5, x1, wback);
-                                emit_or32(dyn, ninst, rex, x1, x5, x3, x4);
+                        if(wback==xRSP && !i64) {
+                            // this is __faststorefence
+                            DMB_ST();
+                        } else {
+                            if(arm64_atomics) {
+                                MOV64xw(x5, i64);
+                                UFLAG_IF {
+                                    LDSETALxw(x5, x1, wback);
+                                    emit_or32(dyn, ninst, rex, x1, x5, x3, x4);
+                                } else {
+                                    STSETLxw(x5, wback);
+                                }
                             } else {
-                                STSETLxw(x5, wback);
+                                MARKLOCK;
+                                LDAXRxw(x1, wback);
+                                emit_or32c(dyn, ninst, rex, x1, i64, x3, x4);
+                                STLXRxw(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
                             }
-                        } else {
-                            MARKLOCK;
-                            LDAXRxw(x1, wback);
-                            emit_or32c(dyn, ninst, rex, x1, i64, x3, x4);
-                            STLXRxw(x3, x1, wback);
-                            CBNZx_MARKLOCK(x3);
+                            SMDMB();
                         }
-                        SMDMB();
                     }
                     break;
                 case 2: //ADC