[DYNAREC] Added F2 0F 7C opcode

3 files changed, 31 insertions, 2 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index e74fa8c7..234dfde2 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -788,6 +788,20 @@
 #define FSUBS(Sd, Sn, Sm)           EMIT(FADDSUB_scalar(0b00, Sm, 1, Sn, Sd))
 #define FSUBD(Dd, Dn, Dm)           EMIT(FADDSUB_scalar(0b01, Dm, 1, Dn, Dd))
 
+// ADD Pair
+#define ADDP_vector(Q, size, Rm, Rn, Rd)    ((Q)<<30 | 0b01110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b10111<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VADDPQ_8(Vd, Vn, Vm)        EMIT(ADDP(1, 0b00, Vm, Vn, Vd))
+#define VADDPQ_16(Vd, Vn, Vm)       EMIT(ADDP(1, 0b01, Vm, Vn, Vd))
+#define VADDPQ_32(Vd, Vn, Vm)       EMIT(ADDP(1, 0b10, Vm, Vn, Vd))
+#define VADDPQ_64(Vd, Vn, Vm)       EMIT(ADDP(1, 0b11, Vm, Vn, Vd))
+#define VADDP_8(Vd, Vn, Vm)         EMIT(ADDP(0, 0b00, Vm, Vn, Vd))
+#define VADDP_16(Vd, Vn, Vm)        EMIT(ADDP(0, 0b01, Vm, Vn, Vd))
+#define VADDP_32(Vd, Vn, Vm)        EMIT(ADDP(0, 0b10, Vm, Vn, Vd))
+
+#define FADDP_vector(Q, sz, Rm, Rn, Rd) ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11010<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VFADDPQS(Vd, Vn, Vm)        EMIT(FADDP_vector(1, 0, Vm, Vn, Vd))
+#define VFADDPQD(Vd, Vn, Vm)        EMIT(FADDP_vector(1, 1, Vm, Vn, Vd))
+
 // MUL
 #define FMUL_vector(Q, sz, Rm, Rn, Rd)  ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11011<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VFMULS(Sd, Sn, Sm)          EMIT(FMUL_vector(0, 0, Sm, Sn, Sd))
diff --git a/src/dynarec/arm64_printer.c b/src/dynarec/arm64_printer.c
index ad36e3c0..a76dda64 100755
--- a/src/dynarec/arm64_printer.c
+++ b/src/dynarec/arm64_printer.c
@@ -883,7 +883,7 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         char s = a.Q?'V':'D';

         char d = sf?'D':'S';

         int n = (a.Q && !sf)?4:2;

-        snprintf(buff, sizeof(buff), "VFADD %c%d.%d%c, %c%d.%d%c, %c%d.%c%d", s, Rd, n, d, s, Rn, n, d, s, Rm, s, d);

+        snprintf(buff, sizeof(buff), "VFADD %c%d.%d%c, %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d, s, Rm, n, d);

         return buff;

     }

     if(isMask(opcode, "00011110ff1mmmmm001010nnnnnddddd", &a)) {

diff --git a/src/dynarec/dynarec_arm64_f20f.c b/src/dynarec/dynarec_arm64_f20f.c
index 195a3e59..7c0fb038 100755
--- a/src/dynarec/dynarec_arm64_f20f.c
+++ b/src/dynarec/dynarec_arm64_f20f.c
@@ -43,7 +43,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     uint8_t nextop;

     uint8_t gd, ed;

     uint8_t wback;

-    int v0;

+    int v0, v1;

     int q0;

     int d0, d1;

     int fixedaddress;

@@ -52,6 +52,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     MAYUSE(d1);

     MAYUSE(q0);

     MAYUSE(v0);

+    MAYUSE(v1);

 

     switch(opcode) {

 

@@ -166,6 +167,20 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VMOVeD(v0, 0, d1, 0);

             break;

 

+        case 0x7C:

+            INST_NAME("HADDPS Gx, Ex");

+            nextop = F8;

+            GETGX(v0);

+            if(MODREG) {

+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));

+            } else {

+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);

+                v1 = fpu_get_scratch(dyn);

+                VLDR128_U12(v1, ed, fixedaddress);

+            }

+            VFADDPQS(v0, v0, v1);

+            break;

+            

         default:

             DEFAULT;

     }