[DYNAREC] Added 66 0F 7C opcode

1 files changed, 24 insertions, 0 deletions

diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index 19af27b9..701f0f6d 100755
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -1381,6 +1381,30 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VCMEQQ_32(v0, v0, q0);

             break;

 

+        case 0x7C:

+            INST_NAME("HADDPD Gx, Ex");

+            nextop = F8;

+            GETGX(q1, 1);

+            GETEX(q0, 0, 0);

+            if(!box64_dynarec_fastnan) {

+                v0 = fpu_get_scratch(dyn);

+                v1 = fpu_get_scratch(dyn);

+                // check if any input value was NAN

+                // but need to mix low/high part

+                VTRNQ1_64(v0, q1, q0);

+                VTRNQ2_64(v1, q1, q0);

+                VFMAXQD(v0, v0, v1);    // propagate NAN

+                VFCMEQQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN

+            }

+            VFADDPQD(q1, q1, q0);

+            if(!box64_dynarec_fastnan) {

+                VFCMEQQD(v1, q1, q1);    // 0 => out is NAN

+                VBICQ(v1, v0, v1);      // forget it in any input was a NAN already

+                VSHLQ_64(v1, v1, 63);   // only keep the sign bit

+                VORRQ(q1, q1, v1);      // NAN -> -NAN

+            }

+            break;

+

         case 0x7E:

             INST_NAME("MOVD Ed,Gx");

             nextop = F8;