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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-03-30 20:25:16 +0000 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-03-30 20:25:16 +0000 |
| commit | 38cf61209e1a5adcb25053b5bac8a3684cc400af (patch) | |
| tree | c1b8ee191f11e7c70fc5cb43517c0de10de23848 /src | |
| parent | 8670e9e5aa8104c88bc850f663ff18ffabe42b4e (diff) | |
| download | box64-38cf61209e1a5adcb25053b5bac8a3684cc400af.tar.gz box64-38cf61209e1a5adcb25053b5bac8a3684cc400af.zip | |
[RV64_DYNAREC] Some more fixes to a few opcode (thanks to cosim)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_00.c | 2 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_emit_math.c | 2 | ||||
| -rw-r--r-- | src/dynarec/rv64/rv64_emitter.h | 2 |
3 files changed, 4 insertions, 2 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_00.c b/src/dynarec/rv64/dynarec_rv64_00.c index a7be6681..61327703 100644 --- a/src/dynarec/rv64/dynarec_rv64_00.c +++ b/src/dynarec/rv64/dynarec_rv64_00.c @@ -834,7 +834,7 @@ uintptr_t dynarec64_00(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni } else { addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, &lock, 1, 0); SMREADLOCK(lock); - LB(x1, ed, fixedaddress); + LBU(x1, ed, fixedaddress); } if(gb2) { MOV64x(x4, ~0xff00); diff --git a/src/dynarec/rv64/dynarec_rv64_emit_math.c b/src/dynarec/rv64/dynarec_rv64_emit_math.c index 65680410..d05ccc24 100644 --- a/src/dynarec/rv64/dynarec_rv64_emit_math.c +++ b/src/dynarec/rv64/dynarec_rv64_emit_math.c @@ -771,7 +771,7 @@ void emit_neg32(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s MV(s3, s1); // s3 = op1 } - NEG(s1, s1); + NEGxw(s1, s1); IFX(X_PEND) { SDxw(s1, xEmu, offsetof(x64emu_t, res)); } diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h index f3d2f4b1..cf9b957a 100644 --- a/src/dynarec/rv64/rv64_emitter.h +++ b/src/dynarec/rv64/rv64_emitter.h @@ -205,6 +205,8 @@ f28–31 ft8–11 FP temporaries Caller #define NOT(rd, rs1) XORI(rd, rs1, -1) // rd = -rs1 #define NEG(rd, rs1) SUB(rd, xZR, rs1) +// rd = -rs1 +#define NEGxw(rd, rs1) SUBxw(rd, xZR, rs1) // rd = rs1 == 0 #define SEQZ(rd, rs1) SLTIU(rd, rs1, 1) // rd = rs1 != 0 |