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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-06-14 18:26:34 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-06-14 18:26:34 +0200 |
| commit | 3cd8b9a44e6fe1e35e8467aa12f1dc4fb12bb57f (patch) | |
| tree | 8d88c3739255b5ce42f355e49794d8fb4d821253 /src | |
| parent | 126119b1fbfd77d5c872130b76bb093d1bf1dbee (diff) | |
| download | box64-3cd8b9a44e6fe1e35e8467aa12f1dc4fb12bb57f.tar.gz box64-3cd8b9a44e6fe1e35e8467aa12f1dc4fb12bb57f.zip | |
[DYNAREC] Added 66 0F F7 opcode
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/dynarec_arm64_660f.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c index 66abfafa..39bf8229 100755 --- a/src/dynarec/dynarec_arm64_660f.c +++ b/src/dynarec/dynarec_arm64_660f.c @@ -1520,7 +1520,23 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n UADDLVQ_16(d1, d0); VMOVeD(q0, 1, d1, 0); break; - + case 0xF7: + INST_NAME("MASKMOVDQU Gx, Ex") + nextop = F8; + GETGX(q0); + GETEX(q1, 0); + v0 = fpu_get_scratch(dyn); + VLDR128_U12(v0, xRDI, 0); + if(MODREG) + v1 = fpu_get_scratch(dyn); // need to preserve the register + else + v1 = q1; + VSSHRQ_8(v1, q1, 7); // get the mask + VBICQ(v0, v0, v1); // mask destination + VANDQ(v1, q0, v1); // mask source + VORRQ(v1, v1, v0); // combine + VSTR128_U12(v1, xRDI, 0); // put back + break; case 0xF8: INST_NAME("PSUBB Gx,Ex"); nextop = F8; |