[ARM64_DYNAREC] Small optims on some shift opcodes

3 files changed, 18 insertions, 22 deletions

diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c
index 1a8020a0..04573de4 100644
--- a/src/dynarec/arm64/dynarec_arm64_00.c
+++ b/src/dynarec/arm64/dynarec_arm64_00.c
@@ -2248,8 +2248,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     UFLAG_IF {  // calculate flags directly
                         CMPSw_U12(x2, 7);
                         B_MARK(cNE);
-                            LSRxw(x3, ed, 7);
-                            ADDxw_REG(x3, x3, ed);
+                            ADDxw_REG_LSR(x3, ed, ed, 7);
                             BFIw(xFlags, x3, F_OF, 1);
                         MARK;
                         BFIw(xFlags, ed, F_CF, 1);
@@ -2384,8 +2383,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     UFLAG_IF {  // calculate flags directly
                         CMPSw_U12(x3, rex.w?63:31);
                         B_MARK(cNE);
-                            LSRxw(x1, ed, rex.w?63:31);
-                            ADDxw_REG(x1, x1, ed);
+                            ADDxw_REG_LSR(x1, ed, ed, rex.w?63:31);
                             BFIw(xFlags, x1, F_OF, 1);
                         MARK;
                         BFIw(xFlags, ed, F_CF, 1);
diff --git a/src/dynarec/arm64/dynarec_arm64_66.c b/src/dynarec/arm64/dynarec_arm64_66.c
index 4d58a850..7bb30c4d 100644
--- a/src/dynarec/arm64/dynarec_arm64_66.c
+++ b/src/dynarec/arm64/dynarec_arm64_66.c
@@ -1119,8 +1119,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     UFLAG_IF {  // calculate flags directly

                         CMPSw_U12(x2, 15);

                         B_MARK(cNE);

-                            LSRxw(x3, ed, 15);

-                            ADDxw_REG(x3, x3, ed);

+                            ADDxw_REG_LSR(x3, ed, ed, 15);

                             BFIw(xFlags, x3, F_OF, 1);

                         MARK;

                         BFIw(xFlags, ed, F_CF, 1);

diff --git a/src/dynarec/arm64/dynarec_arm64_emit_shift.c b/src/dynarec/arm64/dynarec_arm64_emit_shift.c
index 25b7fa54..2ebb5ae5 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_shift.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_shift.c
@@ -322,8 +322,7 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
     }
     if(c<8) {
         IFX(X_CF|X_OF) {
-            LSRw(s3, s1, 8-c);
-            BFIw(xFlags, s3, F_CF, 1);
+            BFXILw(xFlags, s1, 8-c, 1);
         }
         LSLw(s1, s1, c);
 
@@ -390,9 +389,9 @@ void emit_shr8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         SET_DFNONE(s4);
     }
     IFX(X_CF) {
-        SUBw_U12(s3, s2, 1);
-        LSRw_REG(s3, s1, s3);
-        BFIw(xFlags, s3, 0, 1);
+        SUBw_U12(s4, s2, 1);
+        LSRw_REG(s4, s1, s4);
+        BFIw(xFlags, s4, 0, 1);
     }
     IFX(X_OF) {
         CMPSw_U12(s2, 1);   // if s2==1
@@ -463,7 +462,7 @@ void emit_shr8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
     }
 }
 
-// emit SAR8 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch
+// emit SAR8 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch, s2 can be same as s3
 void emit_sar8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -474,9 +473,9 @@ void emit_sar8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         SET_DFNONE(s4);
     }
     IFX(X_CF) {
-        SUBw_U12(s3, s2, 1);
-        ASRw_REG(s3, s1, s3);
-        BFIw(xFlags, s3, 0, 1);
+        SUBw_U12(s4, s2, 1);
+        ASRw_REG(s4, s1, s4);
+        BFIw(xFlags, s4, 0, 1);
     }
     ASRw_REG(s1, s1, s2);
     IFX(X_PEND) {
@@ -660,9 +659,9 @@ void emit_shr16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         SET_DFNONE(s4);
     }
     IFX(X_CF) {
-        SUBw_U12(s3, s2, 1);
-        LSRw_REG(s3, s1, s3);
-        BFIw(xFlags, s3, 0, 1);
+        SUBw_U12(s4, s2, 1);
+        LSRw_REG(s4, s1, s4);
+        BFIw(xFlags, s4, 0, 1);
     }
     IFX(X_OF) {
         CMPSw_U12(s2, 1);   // if s2==1
@@ -733,7 +732,7 @@ void emit_shr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
     }
 }
 
-// emit SAR16 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch
+// emit SAR16 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch, s2 can be same as s3
 void emit_sar16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -744,9 +743,9 @@ void emit_sar16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         SET_DFNONE(s4);
     }
     IFX(X_CF) {
-        SUBw_U12(s3, s2, 1);
-        ASRw_REG(s3, s1, s3);
-        BFIw(xFlags, s3, 0, 1);
+        SUBw_U12(s4, s2, 1);
+        ASRw_REG(s4, s1, s4);
+        BFIw(xFlags, s4, 0, 1);
     }
     ASRw_REG(s1, s1, s2);
     IFX(X_PEND) {