[ARM64_DYNAREC] Removed an unused arg in SET_DFNONE (#2266)

author: Yang Liu <liuyang22@iscas.ac.cn> 2025-01-16 15:20:55 +0800
committer: GitHub <noreply@github.com> 2025-01-16 08:20:55 +0100
commit: 4b8fb0219816f0d22852575e552d266074807dee (patch)
tree: 9e2343fa7f45a0e9911c867e7b454f56eb40d635 /src
parent: 8432f7d8e212c123169f198bc22df7819892a9e9 (diff)
download: box64-4b8fb0219816f0d22852575e552d266074807dee.tar.gz
box64-4b8fb0219816f0d22852575e552d266074807dee.zip
15 files changed, 219 insertions, 212 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c
index e387b8bc..cdf81053 100644
--- a/src/dynarec/arm64/dynarec_arm64_00.c
+++ b/src/dynarec/arm64/dynarec_arm64_00.c
@@ -823,7 +823,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x62:
             if(rex.is32bits) {
                 // BOUND here
-                DEFAULT;                
+                DEFAULT;
             } else {
                 INST_NAME("BOUND Gd, Ed");
                 nextop = F8;
@@ -833,7 +833,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x63:
             if(rex.is32bits) {
                 // ARPL here
-                DEFAULT;                
+                DEFAULT;
             } else {
                 INST_NAME("MOVSXD Gd, Ed");
                 nextop = F8;
@@ -899,7 +899,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 UFLAG_IF {
                     SMULH(x3, ed, x4);
                     MULx(gd, ed, x4);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -923,7 +923,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SMULL(gd, ed, x4);
                     LSRx(x3, gd, 32);
                     MOVw_REG(gd, gd);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -963,7 +963,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 UFLAG_IF {
                     SMULH(x3, ed, x4);
                     MULx(gd, ed, x4);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -987,7 +987,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SMULL(gd, ed, x4);
                     LSRx(x3, gd, 32);
                     MOVw_REG(gd, gd);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -1603,7 +1603,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             ANDw_REG(xFlags, xFlags, x1);
             MOV32w(x1, 0x202);
             ORRw_REG(xFlags, xFlags, x1);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             if(box64_wine || 1) {    // should this be done all the time?
                 TBZ_NEXT(xFlags, F_TF);
                 // go to epilog, TF should trigger at end of next opcode, so using Interpreter only
@@ -1617,7 +1617,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             BICw_REG(xFlags, xFlags, x2);
             ANDw_REG_LSR(x1, x2, xRAX, 8);
             ORRw_REG(xFlags, xFlags, x1);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             break;
         case 0x9F:
             INST_NAME("LAHF");
@@ -3149,8 +3149,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xE6:                      /* OUT Ib, AL */
         case 0xE7:                      /* OUT Ib, EAX */
             INST_NAME(opcode==0xE4?"IN AL, Ib":(opcode==0xE5?"IN EAX, Ib":(opcode==0xE6?"OUT Ib, AL":"OUT Ib, EAX")));
-            if(rex.is32bits && box64_ignoreint3)
-            { 
+            if (rex.is32bits && box64_ignoreint3) {
                 F8;
             } else {
                 if(box64_dynarec_safeflags>1) {
@@ -3437,7 +3436,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     MULw(x1, x2, x1);
                     BFIx(xRAX, x1, 0, 16);
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             CMPSw_REG_LSR(xZR, x1, 8);
                             CSETw(x3, cNE);
@@ -3464,7 +3463,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     MULw(x1, x2, x1);
                     BFIx(xRAX, x1, 0, 16);
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             ASRxw(x2, x1, 8);
                             CMPSw_REG_ASR(x2, x1, 16);
@@ -3503,7 +3502,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     MSUBw(x4, x3, ed, x2);  // x4 = x2 mod ed (i.e. x2 - x3*ed)
                     BFIx(xRAX, x3, 0, 8);
                     BFIx(xRAX, x4, 8, 8);
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -3530,7 +3529,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     MSUBw(x4, x3, ed, x2);  // x4 = x2 mod ed (i.e. x2 - x3*ed)
                     BFIx(xRAX, x3, 0, 8);
                     BFIx(xRAX, x4, 8, 8);
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -3578,7 +3577,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         LSRx(xRDX, xRDX, 32);
                     }
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             CMPSxw_U12(xRDX, 0);
                             CSETw(x3, cNE);
@@ -3612,7 +3611,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         LSRx(xRDX, xRDX, 32);
                     }
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             CMPSxw_REG_ASR(xRDX, xRAX, rex.w?63:31);
                             CSETw(x3, cNE);
@@ -3709,7 +3708,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             MOVx_REG(xRAX, x2);
                         }
                     }
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -3787,7 +3786,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             MOVx_REG(xRAX, x2);
                         }
                     }
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -3799,13 +3798,13 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xF8:
             INST_NAME("CLC");
             SETFLAGS(X_CF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             BFCx(xFlags, F_CF, 1);
             break;
         case 0xF9:
             INST_NAME("STC");
             SETFLAGS(X_CF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             ORRx_mask(xFlags, xFlags, 1, 0, 0); // xFlags | 1
             break;
         case 0xFA:                      /* STI */
diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c
index 9bca36f7..fbb5d399 100644
--- a/src/dynarec/arm64/dynarec_arm64_0f.c
+++ b/src/dynarec/arm64/dynarec_arm64_0f.c
@@ -1670,7 +1670,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xA3:
             INST_NAME("BT Ed, Gd");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETGD;
             if(MODREG) {
@@ -1749,7 +1749,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xAB:
             INST_NAME("BTS Ed, Gd");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETGD;
             if(MODREG) {
@@ -1920,7 +1920,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 UFLAG_IF {
                     SMULH(x3, gd, ed);
                     MULx(gd, gd, ed);
-                    SET_DFNONE(x4);
+                    SET_DFNONE();
                     IFX(X_CF|X_OF) {
                         CMPSx_REG_ASR(x3, gd, 63);
                         CSETw(x3, cNE);
@@ -1940,7 +1940,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SMULL(gd, gd, ed);
                     LSRx(x3, gd, 32);
                     MOVw_REG(gd, gd);
-                    SET_DFNONE(x4);
+                    SET_DFNONE();
                     IFX(X_CF|X_OF) {
                         CMPSw_REG_ASR(x3, gd, 31);
                         CSETw(x3, cNE);
@@ -1993,7 +1993,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xB3:
             INST_NAME("BTR Ed, Gd");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETGD;
             if(MODREG) {
@@ -2073,7 +2073,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 4:
                     INST_NAME("BT Ed, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     gd = x2;
                     if(MODREG) {
                         ed = TO_NAT((nextop & 7) + (rex.b << 3));
@@ -2098,7 +2098,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 5:
                     INST_NAME("BTS Ed, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     if(MODREG) {
                         ed = TO_NAT((nextop & 7) + (rex.b << 3));
                         wback = 0;
@@ -2129,7 +2129,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 6:
                     INST_NAME("BTR Ed, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     if(MODREG) {
                         ed = TO_NAT((nextop & 7) + (rex.b << 3));
                         wback = 0;
@@ -2159,7 +2159,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 7:
                     INST_NAME("BTC Ed, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     if(MODREG) {
                         ed = TO_NAT((nextop & 7) + (rex.b << 3));
                         wback = 0;
@@ -2194,7 +2194,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xBB:
             INST_NAME("BTC Ed, Gd");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETGD;
             if(MODREG) {
@@ -2236,7 +2236,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xBC:
             INST_NAME("BSF Gd, Ed");
             SETFLAGS(X_ZF, SF_SET_DF);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETED(0);
             GETGD;
@@ -2259,7 +2259,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xBD:
             INST_NAME("BSR Gd, Ed");
             SETFLAGS(X_ZF, SF_SET_DF);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETED(0);
             GETGD;
@@ -2460,11 +2460,11 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xC7:
             // rep has no impact here
             nextop = F8;
-            if(MODREG) switch((nextop>>3)&7) { 
+            if(MODREG) switch((nextop>>3)&7) {
             case 6:
                 INST_NAME("RDRAND Ed");
                 SETFLAGS(X_ALL, SF_SET_DF);
-                SET_DFNONE(x1);
+                SET_DFNONE();
                 GETED(0);
                 IFX(X_OF|X_SF|X_ZF|X_PF|X_AF) {
                     MOV32w(x1, (1<<F_OF)|(1<<F_SF)|(1<<F_ZF)|(1<<F_PF)|(1<<F_AF));
@@ -2524,7 +2524,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             case 6:
                 INST_NAME("RDRAND Ed");
                 SETFLAGS(X_ALL, SF_SET_DF);
-                SET_DFNONE(x1);
+                SET_DFNONE();
                 IFX(X_OF|X_SF|X_ZF|X_PF|X_AF) {
                     MOV32w(x1, (1<<F_OF)|(1<<F_SF)|(1<<F_ZF)|(1<<F_PF)|(1<<F_AF));
                     BICw(xFlags, xFlags, x1);
diff --git a/src/dynarec/arm64/dynarec_arm64_64.c b/src/dynarec/arm64/dynarec_arm64_64.c
index affde302..afb497cd 100644
--- a/src/dynarec/arm64/dynarec_arm64_64.c
+++ b/src/dynarec/arm64/dynarec_arm64_64.c
@@ -281,7 +281,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                 UFLAG_IF {
                                     SMULH(x3, gd, ed);
                                     MULx(gd, gd, ed);
-                                    SET_DFNONE(x4);
+                                    SET_DFNONE();
                                     IFX(X_CF|X_OF) {
                                         ASRx(x4, x3, 63);
                                         CMPSx_REG(x3, x4);
@@ -303,7 +303,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                     UFLAG_RES(gd);
                                     LSRx(x3, gd, 32);
                                     MOVw_REG(gd, gd);
-                                    SET_DFNONE(x4);
+                                    SET_DFNONE();
                                     IFX(X_CF|X_OF) {
                                         ASRw(x4, gd, 31);
                                         CMPSw_REG(x3, x4);
@@ -546,7 +546,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 UFLAG_IF {
                     SMULH(x3, ed, x4);
                     MULx(gd, ed, x4);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -571,7 +571,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SMULL(gd, ed, x4);
                     LSRx(x3, gd, 32);
                     MOVw_REG(gd, gd);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -996,7 +996,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             ANDw_REG(xFlags, xFlags, x1);
             MOV32w(x1, 0x202);
             ORRw_REG(xFlags, xFlags, x1);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             if(box64_wine) {    // should this be done all the time?
                 TBZ_NEXT(xFlags, F_TF);
                 // go to epilog, TF should trigger at end of next opcode, so using Interpreter only
@@ -1344,7 +1344,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         LSRx(xRDX, xRDX, 32);
                     }
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             CMPSxw_U12(xRDX, 0);
                             CSETw(x3, cNE);
@@ -1378,7 +1378,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         LSRx(xRDX, xRDX, 32);
                     }
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             ASRxw(x4, xRAX, rex.w?63:31);
                             CMPSxw_REG(xRDX, x4);
@@ -1464,7 +1464,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             MOVx_REG(xRAX, x2);
                         }
                     }
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -1536,7 +1536,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             MOVx_REG(xRAX, x2);
                         }
                     }
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
diff --git a/src/dynarec/arm64/dynarec_arm64_66.c b/src/dynarec/arm64/dynarec_arm64_66.c
index 288691a3..c2a92dc0 100644
--- a/src/dynarec/arm64/dynarec_arm64_66.c
+++ b/src/dynarec/arm64/dynarec_arm64_66.c
@@ -445,7 +445,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             gd=x2;
             GWBACK;
             UFLAG_IF {
-                SET_DFNONE(x4);
+                SET_DFNONE();
                 IFX(X_CF|X_OF) {
                     ASRxw(x1, x2, 16);
                     CMPSw_REG_ASR(x1, x2, 31);
@@ -741,7 +741,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             MOV32w(x1, 0x3F7FD7);
             ANDw_REG(xFlags, xFlags, x1);
             ORRw_mask(xFlags, xFlags, 0b011111, 0);   //mask=0x00000002
-            SET_DFNONE(x1);
+            SET_DFNONE();
             if(box64_wine) {    // should this be done all the time?
                 TBZ_NEXT(xFlags, F_TF);
                 // go to epilog, TF should trigger at end of next opcode, so using Interpreter only
@@ -1282,7 +1282,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
             }
             break;
-        
+
         case 0xD9:
             nextop = F8;
             if(MODREG) {
@@ -1373,7 +1373,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     BFIz(xRAX, x1, 0, 16);
                     BFXILx(xRDX, x1, 16, 16);
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             CMPSw_REG_LSR(xZR, x1, 16);
                             CSETw(x3, cNE);
@@ -1401,7 +1401,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     BFIz(xRAX, x1, 0, 16);
                     BFXILx(xRDX, x1, 16, 16);
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             ASRxw(x2, x1, 16);
                             CMPSw_REG_ASR(x2, x1, 31);
@@ -1441,7 +1441,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     MSUBw(x4, x3, ed, x2);  // x4 = x2 mod ed (i.e. x2 - x3*ed)
                     BFIz(xRAX, x3, 0, 16);
                     BFIz(xRDX, x4, 0, 16);
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -1469,7 +1469,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     MSUBw(x4, x3, ed, x2);  // x4 = x2 mod ed (i.e. x2 - x3*ed)
                     BFIz(xRAX, x3, 0, 16);
                     BFIz(xRDX, x4, 0, 16);
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -1481,13 +1481,13 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xF8:
             INST_NAME("CLC");
             SETFLAGS(X_CF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             BFCx(xFlags, F_CF, 1);
             break;
         case 0xF9:
             INST_NAME("STC");
             SETFLAGS(X_CF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             ORRx_mask(xFlags, xFlags, 1, 0, 0); // xFlags | 1
             break;
 
diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index dc6758da..8867b0a6 100644
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -530,7 +530,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                         MOV32w(x1, (1<<F_PF)|(1<<F_AF)|(1<<F_OF)|(1<<F_SF));
                         BICw_REG(xFlags, xFlags, x1);
                     }
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     break;
 
                 case 0x1C:
@@ -1418,7 +1418,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                         }
                         // flags
                         IFX(X_ALL) {
-                            SET_DFNONE(x4);
+                            SET_DFNONE();
                             IFX(X_CF) {
                                 CMPSw_REG(x1, xZR);
                                 CSETw(x4, cNE);
@@ -2330,7 +2330,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xA3:
             INST_NAME("BT Ew, Gw");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             gd = TO_NAT(((nextop & 0x38) >> 3) + (rex.r << 3)); // GETGD
             if(MODREG) {
@@ -2390,7 +2390,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xAB:
             INST_NAME("BTS Ew, Gw");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             gd = TO_NAT(((nextop & 0x38) >> 3) + (rex.r << 3)); // GETGD
             if(MODREG) {
@@ -2495,7 +2495,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             MULw(x2, x2, x1);
             GWBACK;
             UFLAG_IF {
-                SET_DFNONE(x4);
+                SET_DFNONE();
                 IFX(X_CF|X_OF) {
                     ASRw(x1, x2, 16);
                     CMPSw_REG_ASR(x1, x2, 31);
@@ -2519,7 +2519,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xB3:
             INST_NAME("BTR Ew, Gw");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             gd = TO_NAT(((nextop & 0x38) >> 3) + (rex.r << 3)); // GETGD
             if(MODREG) {
@@ -2595,7 +2595,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                 case 4:
                     INST_NAME("BT Ew, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     gd = x2;
                     GETEW(x1, 1);
                     u8 = F8;
@@ -2613,7 +2613,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                 case 5:
                     INST_NAME("BTS Ew, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     GETEW(x1, 1);
                     u8 = F8;
                     u8&=(rex.w?0x3f:0x0f);
@@ -2633,7 +2633,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                 case 6:
                     INST_NAME("BTR Ew, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     GETEW(x1, 1);
                     u8 = F8;
                     u8&=(rex.w?0x3f:0x0f);
@@ -2652,7 +2652,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                 case 7:
                     INST_NAME("BTC Ew, Ib");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     GETEW(x1, 1);
                     u8 = F8;
                     u8&=(rex.w?0x3f:0x0f);
@@ -2676,7 +2676,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xBB:
             INST_NAME("BTC Ew, Gw");
             SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             gd = TO_NAT(((nextop & 0x38) >> 3) + (rex.r << 3)); // GETGD
             if(MODREG) {
@@ -2713,7 +2713,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xBC:
             INST_NAME("BSF Gw,Ew");
             SETFLAGS(X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETGD;
             GETEW(x1, 0);  // Get EW
@@ -2737,7 +2737,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xBD:
             INST_NAME("BSR Gw,Ew");
             SETFLAGS(X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETGD;
             GETEW(x1, 0);  // Get EW
diff --git a/src/dynarec/arm64/dynarec_arm64_66f30f.c b/src/dynarec/arm64/dynarec_arm64_66f30f.c
index b33c7528..432a6646 100644
--- a/src/dynarec/arm64/dynarec_arm64_66f30f.c
+++ b/src/dynarec/arm64/dynarec_arm64_66f30f.c
@@ -59,7 +59,7 @@ uintptr_t dynarec64_66F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int
         case 0xBD:
             INST_NAME("LZCNT Gw, Ew");
             SETFLAGS(X_CF|X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETEW(x1, 0);
             GETGW(x2);
diff --git a/src/dynarec/arm64/dynarec_arm64_67.c b/src/dynarec/arm64/dynarec_arm64_67.c
index f4f5cabf..f7e41c3e 100644
--- a/src/dynarec/arm64/dynarec_arm64_67.c
+++ b/src/dynarec/arm64/dynarec_arm64_67.c
@@ -58,7 +58,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 
 
     while(opcode==0x67) opcode = F8;
-    
+
     // reset rex after 67
     GETREX();
 
@@ -928,7 +928,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 UFLAG_IF {
                     SMULH(x3, ed, x4);
                     MULx(gd, ed, x4);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -952,7 +952,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SMULL(gd, ed, x4);
                     LSRx(x3, gd, 32);
                     MOVw_REG(gd, gd);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
@@ -1476,7 +1476,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         LSRx(xRDX, xRDX, 32);
                     }
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             CMPSxw_U12(xRDX, 0);
                             CSETw(x3, cNE);
@@ -1510,7 +1510,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         LSRx(xRDX, xRDX, 32);
                     }
                     UFLAG_IF {
-                        SET_DFNONE(x4);
+                        SET_DFNONE();
                         IFX(X_CF|X_OF) {
                             CMPSxw_REG_ASR(xRDX, xRAX, rex.w?63:31);
                             CSETw(x3, cNE);
@@ -1565,7 +1565,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             MOVx_REG(xRAX, x2);
                         }
                     }
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
@@ -1607,7 +1607,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             MOVx_REG(xRAX, x2);
                         }
                     }
-                    SET_DFNONE(x2);
+                    SET_DFNONE();
                     IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
                         if(box64_dynarec_test) {
                             MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
diff --git a/src/dynarec/arm64/dynarec_arm64_emit_logic.c b/src/dynarec/arm64/dynarec_arm64_emit_logic.c
index 363b53d7..6253eee5 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_logic.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_logic.c
@@ -28,7 +28,7 @@ void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3,
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_or64:d_or32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     ORRxw_REG(s1, s1, s2);
     IFX(X_PEND) {
@@ -82,7 +82,7 @@ void emit_or32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_or64:d_or32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     ORRxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
     IFX(X_PEND) {
@@ -131,7 +131,7 @@ void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_xor64:d_xor32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     EORxw_REG(s1, s1, s2);
     IFX(X_PEND) {
@@ -185,7 +185,7 @@ void emit_xor32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_xor64:d_xor32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     if(!mask) {
         MVNxw_REG(s1, s1);
@@ -238,7 +238,7 @@ void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_and64:d_and32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_ZF|X_SF|X_CF|X_OF) {
         ANDSxw_REG(s1, s1, s2);
@@ -290,7 +290,7 @@ void emit_and32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_and64:d_and32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_ZF|X_SF|X_CF|X_OF) {
         ANDSxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
@@ -337,7 +337,7 @@ void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     IFX(X_PEND) {
         SET_DF(s4, d_or8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     ORRw_REG(s1, s1, s2);
     IFX(X_PEND) {
@@ -365,7 +365,7 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4)
     IFX(X_PEND) {
         SET_DF(s4, d_or8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
     IFX(X_PEND) {
@@ -388,7 +388,7 @@ void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     IFX(X_PEND) {
         SET_DF(s4, d_xor8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     EORx_REG(s1, s1, s2);
     IFX(X_PEND) {
@@ -416,7 +416,7 @@ void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
     IFX(X_PEND) {
         SET_DF(s4, d_xor8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
     IFX(X_PEND) {
@@ -439,7 +439,7 @@ void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     IFX(X_PEND) {
         SET_DF(s4, d_and8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_ZF) {
         ANDSw_REG(s1, s1, s2);
@@ -484,7 +484,7 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
     IFX(X_PEND) {
         SET_DF(s4, d_and8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_ZF) {
         ANDSw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
@@ -524,7 +524,7 @@ void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     IFX(X_PEND) {
         SET_DF(s4, d_or16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     ORRw_REG(s1, s1, s2);
     IFX(X_PEND) {
@@ -552,7 +552,7 @@ void emit_or16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s4
     IFX(X_PEND) {
         SET_DF(s4, d_or16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
     IFX(X_PEND) {
@@ -575,7 +575,7 @@ void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     IFX(X_PEND) {
         SET_DF(s4, d_xor16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     EORw_REG(s1, s1, s2);
     IFX(X_PEND) {
@@ -603,7 +603,7 @@ void emit_xor16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s
     IFX(X_PEND) {
         SET_DF(s4, d_xor16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
     IFX(X_PEND) {
@@ -627,7 +627,7 @@ void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     IFX(X_PEND) {
         SET_DF(s4, d_and16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_ZF) {
         ANDSw_REG(s1, s1, s2);
@@ -672,7 +672,7 @@ void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s
     IFX(X_PEND) {
         SET_DF(s4, d_and16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_ZF) {
         ANDSw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
diff --git a/src/dynarec/arm64/dynarec_arm64_emit_math.c b/src/dynarec/arm64/dynarec_arm64_emit_math.c
index d7ac7da5..34687f8d 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_math.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_math.c
@@ -30,7 +30,7 @@ void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_add64:d_add32b);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         ORRxw_REG(s3, s1, s2);    // s3 = op1 | op2
@@ -100,7 +100,7 @@ void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_add64:d_add32b);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         IFX(X_PEND) {} else {MOV64xw(s5, c);}
@@ -168,7 +168,7 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_sub64:d_sub32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         ORNxw_REG(s3, s2, s1);  // s3 = ~op1 | op2
@@ -241,7 +241,7 @@ void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_sub64:d_sub32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         IFX(X_PEND) {} else {MOV64xw(s5, c);}
@@ -312,7 +312,7 @@ void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_add8b);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF | X_OF) {
         ORRw_REG(s3, s1, s2);    // s3 = op1 | op2
@@ -378,7 +378,7 @@ void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
         STRB_U12(s4, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_add8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF | X_OF) {
         IFX(X_PEND) {} else {MOV32w(s4, c);}
@@ -421,7 +421,7 @@ void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sub8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF|X_OF|X_CF) {
         MVNw_REG(s3, s1);
@@ -468,7 +468,7 @@ void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
         STRB_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sub8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF|X_OF|X_CF) {
         MVNw_REG(s3, s1);
@@ -515,7 +515,7 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_add16b);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         ORRw_REG(s3, s1, s2);    // s3 = op1 | op2
@@ -573,7 +573,7 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 }
 
 // emit ADD16 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
-//void emit_add16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
+// void emit_add16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
 //        MOVW(s3, c);
@@ -581,7 +581,7 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
 //        SET_DF(s4, d_add16);
 //    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
+//        SET_DFNONE();
 //    }
 //    IFX(X_AF | X_OF) {
 //        MOV_REG(s4, s1);
@@ -648,7 +648,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sub16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF|X_OF|X_CF) {
         ORNw_REG(s3, s2, s1);    // s3 = ~op1 | op2
@@ -683,7 +683,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 }
 
 // emit SUB16 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
-//void emit_sub16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
+// void emit_sub16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
 //        MOVW(s3, c);
@@ -691,7 +691,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
 //        SET_DF(s4, d_sub16);
 //    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
+//        SET_DFNONE();
 //    }
 //    IFX(X_AF|X_OF|X_CF) {
 //        MVN_REG_LSL_IMM5(s4, s1, 0);
@@ -750,7 +750,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 // emit INC32 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4)
 {
-    SET_DFNONE(s4);
+    SET_DFNONE();
     IFX(X_AF) {
         if(rex.w) {
             ORRx_mask(s3, s1, 1, 0, 0);          // s3 = op1 | op2
@@ -797,7 +797,7 @@ void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
 // emit INC8 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
-    SET_DFNONE(s3);
+    SET_DFNONE();
     IFX(X_AF | X_OF) {
         ORRw_mask(s3, s1, 0, 0);     // s3 = op1 | op2
         ANDw_mask(s4, s1, 0, 0);        // s4 = op1 & op2
@@ -825,7 +825,7 @@ void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 // emit INC16 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
-    SET_DFNONE(s3);
+    SET_DFNONE();
     IFX(X_AF | X_OF) {
         ORRw_mask(s3, s1, 0, 0);    // s3 = op1 | op2
         ANDw_mask(s4, s1, 0, 0);    // s4 = op1 & op2
@@ -853,7 +853,7 @@ void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 // emit DEC32 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4)
 {
-    SET_DFNONE(s4);
+    SET_DFNONE();
     IFX(X_AF) {
         MVNxw_REG(s3, s1);
         if(rex.w) {
@@ -901,7 +901,7 @@ void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
 // emit DEC8 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_dec8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
-    SET_DFNONE(s3);
+    SET_DFNONE();
     IFX(X_AF|X_OF) {
         MVNw_REG(s3, s1);
         ANDw_mask(s4, s3, 0, 0);        // s4 = ~op1 & op2
@@ -943,7 +943,7 @@ void emit_dec8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 // emit DEC16 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
-    SET_DFNONE(s3);
+    SET_DFNONE();
     IFX(X_AF|X_OF) {
         MVNw_REG(s4, s1);
     }
@@ -991,7 +991,7 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_adc64:d_adc32b);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
         if(INVERTED_CARRY_BEFORE) {
@@ -1056,7 +1056,7 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 }
 
 // emit ADC32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
-//void emit_adc32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+// void emit_adc32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
 //        MOV32(s3, c);
@@ -1064,7 +1064,7 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 //        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
 //        SET_DF(s4, d_adc32);
 //    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
+//        SET_DFNONE();
 //    }
 //    IFX(X_AF) {
 //        MOV_REG(s4, s1);
@@ -1134,7 +1134,7 @@ void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_adc8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
         if(INVERTED_CARRY_BEFORE) {
@@ -1198,7 +1198,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_adc16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
         if(INVERTED_CARRY_BEFORE) {
@@ -1246,7 +1246,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 }
 
 // emit ADC16 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
-//void emit_adc16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
+// void emit_adc16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
 //        MOVW(s3, c);
@@ -1254,7 +1254,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
 //        SET_DF(s3, d_adc16);
 //    } else IFX(X_ALL) {
-//        SET_DFNONE(s3);
+//        SET_DFNONE();
 //    }
 //    IFX(X_AF | X_OF) {
 //        MOV_REG(s4, s1);
@@ -1321,7 +1321,7 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_sbb64:d_sbb32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
         if(!INVERTED_CARRY_BEFORE) {
@@ -1390,7 +1390,7 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 }
 
 // emit SBB32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
-//void emit_sbb32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+// void emit_sbb32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
 //        MOV32(s3, c);
@@ -1398,7 +1398,7 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 //        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
 //        SET_DF(s4, d_sbb32);
 //    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
+//        SET_DFNONE();
 //    }
 //    IFX(X_AF) {
 //        MVN_REG_LSL_IMM5(s4, s1, 0);
@@ -1470,7 +1470,7 @@ void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sbb8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
         if(!INVERTED_CARRY_BEFORE) {
@@ -1535,7 +1535,7 @@ void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sbb16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
         if(!INVERTED_CARRY_BEFORE) {
@@ -1584,7 +1584,7 @@ void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 }
 
 // emit SBB16 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
-//void emit_sbb16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
+// void emit_sbb16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
 //        MOVW(s3, c);
@@ -1592,7 +1592,7 @@ void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
 //        SET_DF(s3, d_sbb16);
 //    } else IFX(X_ALL) {
-//        SET_DFNONE(s3);
+//        SET_DFNONE();
 //    }
 //    IFX(X_AF|X_OF|X_CF) {
 //        MVN_REG_LSL_IMM5(s4, s1, 0);
@@ -1657,7 +1657,7 @@ void emit_neg32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         SET_DF(s3, rex.w?d_neg64:d_neg32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         TSTxw_REG(s1, s1);
@@ -1710,7 +1710,7 @@ void emit_neg16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         SET_DF(s3, d_neg16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         TSTw_REG(s1, s1);
@@ -1759,7 +1759,7 @@ void emit_neg8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         SET_DF(s3, d_neg8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         TSTw_REG(s1, s1);
diff --git a/src/dynarec/arm64/dynarec_arm64_emit_shift.c b/src/dynarec/arm64/dynarec_arm64_emit_shift.c
index 96ab49bc..e6bac6eb 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_shift.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_shift.c
@@ -33,7 +33,7 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shl64:d_shl32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF | X_OF) {
         MOV32w(s4, rex.w?64:32);
@@ -88,7 +88,7 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shl64:d_shl32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF|X_OF) {
         LSRxw(s3, s1, (rex.w?64:32)-c);
@@ -150,7 +150,7 @@ void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shr64:d_shr32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         SUBxw_U12(s3, s2, 1);
@@ -203,7 +203,7 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shr64:d_shr32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         if(c==1) {
@@ -261,7 +261,7 @@ void emit_sar32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_sar64:d_sar32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         SUBxw_U12(s3, s2, 1);
@@ -311,7 +311,7 @@ void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_sar64:d_sar32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         ASRxw(s3, s1, c-1);
@@ -362,7 +362,7 @@ void emit_shl8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF | X_OF) {
         MOV32w(s4, 8);
@@ -402,7 +402,7 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
         STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     if(c<8) {
         IFX(X_CF|X_OF) {
@@ -474,7 +474,7 @@ void emit_shr8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         SUBw_U12(s4, s2, 1);
@@ -511,7 +511,7 @@ void emit_shr8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
         STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         if(c==1) {
@@ -551,7 +551,7 @@ void emit_sar8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         SUBw_U12(s4, s2, 1);
@@ -587,7 +587,7 @@ void emit_sar8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
         STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar8);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     if(c<8) IFX(X_CF) {
         BFXILw(xFlags, s1, c-1, 1);
@@ -633,7 +633,7 @@ void emit_shl16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF | X_OF) {
         MOV32w(s4, 16);
@@ -672,7 +672,7 @@ void emit_shl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     if(c<16) {
         IFX(X_CF|X_OF) {
@@ -745,7 +745,7 @@ void emit_shr16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         SUBw_U12(s4, s2, 1);
@@ -783,7 +783,7 @@ void emit_shr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         if(c==1) {
@@ -823,7 +823,7 @@ void emit_sar16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         SUBw_U12(s4, s2, 1);
@@ -859,7 +859,7 @@ void emit_sar16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         ASRw(s3, s1, c-1);
@@ -889,7 +889,7 @@ void emit_rol32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
 
     if (!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     RORxw(s1, s1, (rex.w?64:32)-c);
     IFX(X_CF) {
@@ -912,7 +912,7 @@ void emit_ror32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
 
     if (!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     RORxw(s1, s1, c);
     IFX(X_CF) {
@@ -936,7 +936,7 @@ void emit_rol8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
 
     if (!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     if(c&7) {
         int rc = 8-(c&7);
@@ -963,7 +963,7 @@ void emit_ror8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
 
     if (!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     if(c&7) {
         ORRw_REG_LSL(s1, s1, s1, 8);
@@ -990,7 +990,7 @@ void emit_rol16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
 
     if (!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     if(c&15) {
         int rc = 16-(c&15);
@@ -1017,7 +1017,7 @@ void emit_ror16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
 
     if (!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     if(c&15) {
         ORRw_REG_LSL(s1, s1, s1, 16);
@@ -1044,7 +1044,7 @@ void emit_rcl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
 
     if (!(c%9)) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     c%=9;
     BFIw(s1, xFlags, 8, 1); // insert cf
@@ -1079,7 +1079,7 @@ void emit_rcr8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
 
     if (!(c%9)) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     c%=9;
     IFX(X_OF) {
@@ -1110,7 +1110,7 @@ void emit_rcl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
 
     if (!(c%17)) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     c%=17;
     BFIw(s1, xFlags, 16, 1); // insert cf
@@ -1143,7 +1143,7 @@ void emit_rcr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
 
     if (!(c%17)) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     c%=17;
     BFIw(s1, xFlags, 16, 1); // insert cf
@@ -1174,7 +1174,7 @@ void emit_rcl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
 
     if(!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     IFX(X_OF|X_CF) {
         LSRxw_IMM(s3, s1, (rex.w?64:32)-c);
@@ -1206,7 +1206,7 @@ void emit_rcr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
 
     if(!c) return;
 
-    SET_DFNONE(s4);
+    SET_DFNONE();
 
     IFX(X_OF) {
         if(c==1) {
@@ -1241,7 +1241,7 @@ void emit_shrd32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, uint
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shrd64:d_shrd32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     if(!c) {
         IFX(X_PEND) {
@@ -1300,7 +1300,7 @@ void emit_shld32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, uint
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shld64:d_shld32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         BFXILx(xFlags, s1, (rex.w?64:32)-c, 1);
@@ -1355,7 +1355,7 @@ void emit_shrd32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
         // same flags computation as with shl64/shl32
         SET_DF(s4, rex.w?d_shrd64:d_shrd32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         SUBw_U12(s3, s5, 1);
@@ -1421,7 +1421,7 @@ void emit_shld32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
         STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shld64:d_shld32);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     MOV32w(s3, (rex.w?64:32));
     SUBw_REG(s3, s3, s5);
@@ -1490,7 +1490,7 @@ void emit_shrd16c(dynarec_arm_t* dyn, int ninst, int s1, int s2, uint32_t c, int
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shrd16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     if(!c) {
         IFX(X_PEND) {
@@ -1536,7 +1536,7 @@ void emit_shrd16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s5, int s3,
         // same flags computation as with shl64/shl32
         SET_DF(s4, d_shrd16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     ORRw_REG_LSL(s1, s1, s2, 16);   // create concat first
     IFX(X_CF) {
@@ -1579,7 +1579,7 @@ void emit_shld16c(dynarec_arm_t* dyn, int ninst, int s1, int s2, uint32_t c, int
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shld16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     if(c==0) {
         IFX(X_OF) {
@@ -1629,7 +1629,7 @@ void emit_shld16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s5, int s3,
         STRH_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shld16);
     } else IFX(X_ALL) {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         ORRw_REG_LSL(s4, s2, s1, 16);
diff --git a/src/dynarec/arm64/dynarec_arm64_emit_tests.c b/src/dynarec/arm64/dynarec_arm64_emit_tests.c
index 9933934f..75d1bee0 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_tests.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_tests.c
@@ -30,7 +30,7 @@ void emit_cmp32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_cmp64:d_cmp32);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         ORNxw_REG(s3, s2, s1);  // s3 = ~op1 | op2
@@ -88,7 +88,7 @@ void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
         SET_DF(s4, rex.w?d_cmp64:d_cmp32);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     SUBSxw_U12(s3, s1, 0);   // res = s1 - 0
     // and now the tricky ones (and mostly unused), PF and AF
@@ -134,7 +134,7 @@ void emit_cmp16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, i
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_cmp16);
     } else {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         ORNw_REG(s3, s2, s1);  // s3 = ~op1 | op2
@@ -206,7 +206,7 @@ void emit_cmp16_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
         SET_DF(s3, d_cmp16);
     } else {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     // bc = (res & (~d | s)) | (~d & s) = 0
     IFX(X_CF | X_AF | X_OF) {
@@ -227,7 +227,7 @@ void emit_cmp8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, in
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_cmp8);
     } else {
-        SET_DFNONE(s3);
+        SET_DFNONE();
     }
     IFX(X_AF) {
         ORNw_REG(s3, s2, s1);  // s3 = ~op1 | op2
@@ -298,7 +298,7 @@ void emit_cmp8_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
         SET_DF(s3, d_cmp8);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     // bc = (res & (~d | s)) | (~d & s) = 0
     IFX(X_CF | X_AF | X_OF) {
@@ -318,7 +318,7 @@ void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
     IFX_PENDOR0 {
         SET_DF(s3, rex.w?d_tst64:d_tst32);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         IFNATIVE(NF_CF) {} else {
@@ -362,7 +362,7 @@ void emit_test32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, i
     IFX_PENDOR0 {
         SET_DF(s3, rex.w?d_tst64:d_tst32);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF) {
         IFNATIVE(NF_CF) {} else {
@@ -410,7 +410,7 @@ void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4,
     IFX_PENDOR0 {
         SET_DF(s3, d_tst16);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF|X_ZF|X_SF|X_OF) {
         LSLw(s5, s1, 16);
@@ -458,7 +458,7 @@ void emit_test16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
     IFX_PENDOR0 {
         SET_DF(s3, d_tst16);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF|X_ZF|X_SF|X_OF) {
         LSLw(s5, s1, 16);
@@ -517,7 +517,7 @@ void emit_test8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, i
     IFX_PENDOR0 {
         SET_DF(s3, d_tst8);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF|X_ZF|X_SF|X_OF) {
         LSLw(s5, s1, 24);
@@ -565,7 +565,7 @@ void emit_test8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
     IFX_PENDOR0 {
         SET_DF(s3, d_tst8);
     } else {
-        SET_DFNONE(s4);
+        SET_DFNONE();
     }
     IFX(X_CF|X_ZF|X_SF|X_OF) {
         LSLw(s5, s1, 24);
diff --git a/src/dynarec/arm64/dynarec_arm64_f0.c b/src/dynarec/arm64/dynarec_arm64_f0.c
index 00f8adc8..561653ce 100644
--- a/src/dynarec/arm64/dynarec_arm64_f0.c
+++ b/src/dynarec/arm64/dynarec_arm64_f0.c
@@ -77,7 +77,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 if(arm64_atomics) {
                     UFLAG_IF {
                         LDADDALB(x2, x1, wback);
-                        emit_add8(dyn, ninst, x1, x2, x4, x5);    
+                        emit_add8(dyn, ninst, x1, x2, x4, x5);
                     } else {
                         STADDLB(x2, wback);
                     }
@@ -114,7 +114,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 if(arm64_atomics) {
                     UFLAG_IF {
                         LDADDALxw(gd, x1, wback);
-                        emit_add32(dyn, ninst, rex, x1, gd, x3, x4);    
+                        emit_add32(dyn, ninst, rex, x1, gd, x3, x4);
                     } else {
                         STADDLxw(gd, wback);
                     }
@@ -164,7 +164,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 if(arm64_atomics) {
                     LDSETALB(x2, x1, wback);
                     UFLAG_IF {
-                        emit_or8(dyn, ninst, x1, x2, x4, x5);    
+                        emit_or8(dyn, ninst, x1, x2, x4, x5);
                     }
                 } else {
                     MARKLOCK;
@@ -189,7 +189,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 if(arm64_atomics) {
                     LDSETALxw(gd, x1, wback);
                     UFLAG_IF {
-                        emit_or32(dyn, ninst, rex, x1, gd, x3, x4);    
+                        emit_or32(dyn, ninst, rex, x1, gd, x3, x4);
                     }
                 } else {
                     MARKLOCK;
@@ -209,7 +209,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 0xAB:
                     INST_NAME("LOCK BTS Ed, Gd");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     nextop = F8;
                     GETGD;
                     if(MODREG) {
@@ -407,7 +407,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 0xB3:
                     INST_NAME("LOCK BTR Ed, Gd");
                     SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                    SET_DFNONE(x1);
+                    SET_DFNONE();
                     nextop = F8;
                     GETGD;
                     if(MODREG) {
@@ -461,7 +461,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     case 4:
                         INST_NAME("LOCK BT Ed, Ib");
                         SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                        SET_DFNONE(x1);
+                        SET_DFNONE();
                         gd = x2;
                         if(MODREG) {
                             ed = TO_NAT((nextop & 7) + (rex.b << 3));
@@ -496,7 +496,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     case 5:
                         INST_NAME("LOCK BTS Ed, Ib");
                         SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                        SET_DFNONE(x1);
+                        SET_DFNONE();
                         if(MODREG) {
                             ed = TO_NAT((nextop & 7) + (rex.b << 3));
                             wback = 0;
@@ -543,7 +543,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     case 6:
                         INST_NAME("LOCK BTR Ed, Ib");
                         SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                        SET_DFNONE(x1);
+                        SET_DFNONE();
                         if(MODREG) {
                             ed = TO_NAT((nextop & 7) + (rex.b << 3));
                             wback = 0;
@@ -585,7 +585,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     case 7:
                         INST_NAME("LOCK BTC Ed, Ib");
                         SETFLAGS(X_ALL&~X_ZF, SF_SUBSET);
-                        SET_DFNONE(x1);
+                        SET_DFNONE();
                         if(MODREG) {
                             ed = TO_NAT((nextop & 7) + (rex.b << 3));
                             wback = 0;
@@ -770,7 +770,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             if(arm64_uscat) {
                                 if(rex.w) {
                                     TSTx_mask(wback, 1, 0, 3);
-                                    B_MARK2(cNE);    
+                                    B_MARK2(cNE);
                                 } else {
                                     ANDx_mask(x2, wback, 1, 0, 3);  // mask = F
                                     CMPSw_U12(x2, 8);
@@ -1040,7 +1040,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 if(arm64_atomics) {
                     UFLAG_IF {
                         LDEORALxw(gd, x1, wback);
-                        emit_xor32(dyn, ninst, rex, x1, gd, x3, x4);    
+                        emit_xor32(dyn, ninst, rex, x1, gd, x3, x4);
                     } else {
                         STEORLxw(gd, wback);
                     }
@@ -1260,7 +1260,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                             MOV32w(x2, u8);
                             UFLAG_IF {
                                 LDEORALB(x2, x1, wback);
-                                emit_xor8(dyn, ninst, x1, x2, x3, x4);    
+                                emit_xor8(dyn, ninst, x1, x2, x3, x4);
                             } else {
                                 STEORLB(x2, wback);
                             }
@@ -1369,7 +1369,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                 emit_or32(dyn, ninst, rex, x1, x5, x3, x4);
                             } else {
                                 STSETLxw(x5, wback);
-                            } 
+                            }
                         } else {
                             MARKLOCK;
                             LDAXRxw(x1, wback);
diff --git a/src/dynarec/arm64/dynarec_arm64_f30f.c b/src/dynarec/arm64/dynarec_arm64_f30f.c
index 38c62bde..bbe987e4 100644
--- a/src/dynarec/arm64/dynarec_arm64_f30f.c
+++ b/src/dynarec/arm64/dynarec_arm64_f30f.c
@@ -470,7 +470,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xB8:
             INST_NAME("POPCNT Gd, Ed");
             SETFLAGS(X_ALL, SF_SET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             v1 = fpu_get_scratch(dyn, ninst);
             GETGD;
@@ -506,7 +506,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                     else {
                         CSETw(x1, cEQ);
                         BFIw(xFlags, x1, F_ZF, 1);
-                    }                    
+                    }
                 }
             }
             break;
@@ -514,7 +514,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xBC:
             INST_NAME("TZCNT Gd, Ed");
             SETFLAGS(X_CF|X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETED(0);
             GETGD;
@@ -534,7 +534,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xBD:
             INST_NAME("LZCNT Gd, Ed");
             SETFLAGS(X_CF|X_ZF, SF_SUBSET);
-            SET_DFNONE(x1);
+            SET_DFNONE();
             nextop = F8;
             GETED(0);
             GETGD;
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.c b/src/dynarec/arm64/dynarec_arm64_helper.c
index 2a51678e..d48cad33 100644
--- a/src/dynarec/arm64/dynarec_arm64_helper.c
+++ b/src/dynarec/arm64/dynarec_arm64_helper.c
@@ -715,7 +715,7 @@ void iret_to_epilog(dynarec_arm_t* dyn, int ninst, int is32bits, int is64bits)
     MAYUSE(j64);
     MESSAGE(LOG_DUMP, "IRet to epilog\n");
     SMEND();
-    SET_DFNONE(x2);
+    SET_DFNONE();
     // POP IP
     NOTEST(x2);
     if(is64bits) {
@@ -734,7 +734,7 @@ void iret_to_epilog(dynarec_arm_t* dyn, int ninst, int is32bits, int is64bits)
     MOV32w(x1, 0x3F7FD7);
     ANDx_REG(xFlags, xFlags, x1);
     ORRx_mask(xFlags, xFlags, 1, 0b111111, 0); // xFlags | 0b10
-    SET_DFNONE(x1);
+    SET_DFNONE();
     if(is32bits) {
         ANDw_mask(x2, x2, 0, 7);   // mask 0xff
         // check if return segment is 64bits, then restore rsp too
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h
index 266005f2..5c5d7ec7 100644
--- a/src/dynarec/arm64/dynarec_arm64_helper.h
+++ b/src/dynarec/arm64/dynarec_arm64_helper.h
@@ -975,7 +975,7 @@
         /* greater than leave 0 */                                          \
         ORRw_REG(xFlags, xFlags, s1);                                       \
     }                                                                       \
-    SET_DFNONE(s1);                                                         \
+    SET_DFNONE();                                                           \
 
 #ifndef IF_UNALIGNED
 #define IF_UNALIGNED(A)    if(is_addr_unaligned(A))
@@ -1081,18 +1081,26 @@
     x87_do_pop(dyn, ninst, scratch)
 #endif
 
-#define SET_DFNONE(S)    do {dyn->f.dfnone_here=1; if(!dyn->f.dfnone) {STRw_U12(wZR, xEmu, offsetof(x64emu_t, df)); dyn->f.dfnone=1;}} while(0);
-#define SET_DF(S, N)        \
-    if((N)!=d_none) {       \
-        MOVZw(S, (N));      \
-        STRw_U12(S, xEmu, offsetof(x64emu_t, df)); \
-        if(dyn->f.pending==SF_PENDING && dyn->insts[ninst].x64.need_after && !(dyn->insts[ninst].x64.need_after&X_PEND)) {  \
-            CALL_(UpdateFlags, -1, 0);              \
-            dyn->f.pending = SF_SET;                \
-            SET_NODF();     \
-        }                   \
-        dyn->f.dfnone=0;    \
-    } else SET_DFNONE(S)
+#define SET_DFNONE()                                     \
+    do {                                                 \
+        dyn->f.dfnone_here = 1;                          \
+        if (!dyn->f.dfnone) {                            \
+            STRw_U12(wZR, xEmu, offsetof(x64emu_t, df)); \
+            dyn->f.dfnone = 1;                           \
+        }                                                \
+    } while (0);
+#define SET_DF(S, N)                                                                                                            \
+    if ((N) != d_none) {                                                                                                        \
+        MOVZw(S, (N));                                                                                                          \
+        STRw_U12(S, xEmu, offsetof(x64emu_t, df));                                                                              \
+        if (dyn->f.pending == SF_PENDING && dyn->insts[ninst].x64.need_after && !(dyn->insts[ninst].x64.need_after & X_PEND)) { \
+            CALL_(UpdateFlags, -1, 0);                                                                                          \
+            dyn->f.pending = SF_SET;                                                                                            \
+            SET_NODF();                                                                                                         \
+        }                                                                                                                       \
+        dyn->f.dfnone = 0;                                                                                                      \
+    } else                                                                                                                      \
+        SET_DFNONE()
 #ifndef SET_NODF
 #define SET_NODF()          dyn->f.dfnone = 0
 #endif
author	Yang Liu <liuyang22@iscas.ac.cn>	2025-01-16 15:20:55 +0800
committer	GitHub <noreply@github.com>	2025-01-16 08:20:55 +0100
commit	4b8fb0219816f0d22852575e552d266074807dee (patch)
tree	9e2343fa7f45a0e9911c867e7b454f56eb40d635 /src
parent	8432f7d8e212c123169f198bc22df7819892a9e9 (diff)
download	box64-4b8fb0219816f0d22852575e552d266074807dee.tar.gz box64-4b8fb0219816f0d22852575e552d266074807dee.zip