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authorptitSeb <sebastien.chev@gmail.com>2024-08-30 10:02:49 +0200
committerptitSeb <sebastien.chev@gmail.com>2024-08-30 10:02:49 +0200
commit4dcf14d02661948eb3322f24cbba72a1bd944fc9 (patch)
treefc91d3e2a01dee7a263baa348ab3a627f1e4db75 /src
parent854ee95d695d99c69eaeef1b90f93fc0191ffa24 (diff)
downloadbox64-4dcf14d02661948eb3322f24cbba72a1bd944fc9.tar.gz
box64-4dcf14d02661948eb3322f24cbba72a1bd944fc9.zip
[ARM64_DYNAREC] Added 67 F3 0F 38 F6 opcode (for #1775)
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_67.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_67.c b/src/dynarec/arm64/dynarec_arm64_67.c
index 6823a6d4..b38f9788 100644
--- a/src/dynarec/arm64/dynarec_arm64_67.c
+++ b/src/dynarec/arm64/dynarec_arm64_67.c
@@ -220,6 +220,39 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     }

                     break;

 

+                case 0x38:  /* MAP 0F38 */

+                    opcode = F8;

+                    switch(opcode) {

+                        case 0xF6:

+                            switch(rep) {

+                                case 2:

+                                    INST_NAME("ADOX Gd, Ed");

+                                    nextop = F8;

+                                    READFLAGS(X_OF);

+                                    SETFLAGS(X_OF, SF_SUBSET);

+                                    GETED32(0);

+                                    GETGD;

+                                    MRS_nzvc(x3);

+                                    LSRw(x4, xFlags, F_OF);

+                                    BFIx(x3, x4, 29, 1); // set C

+                                    MSR_nzvc(x3);      // load CC into ARM CF

+                                    IFX(X_OF) {

+                                        ADCSxw_REG(gd, gd, ed);

+                                        CSETw(x3, cCS);

+                                        BFIw(xFlags, x3, F_OF, 1);

+                                    } else {

+                                        ADCxw_REG(gd, gd, ed);

+                                    }

+                                    break;

+                                default:

+                                    DEFAULT;

+                            }

+                            break;

+                        default:

+                            DEFAULT;

+                    }

+                    break;

+

                 case 0x6F:

                     switch(rep) {

                         case 0: