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| author | ptitSeb <sebastien.chev@gmail.com> | 2025-01-05 14:57:24 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2025-01-05 14:57:24 +0100 |
| commit | 5a35184ba7d01636323eee763717db9f2781ff5a (patch) | |
| tree | 2e1cc009bd433913485a2419db17f8bf6c2d8735 /src | |
| parent | db801da6580e8a187350e37c39ba69507e5b470c (diff) | |
| download | box64-5a35184ba7d01636323eee763717db9f2781ff5a.tar.gz box64-5a35184ba7d01636323eee763717db9f2781ff5a.zip | |
[INTERPRETER] Added a few more cpu extension and associated opcodes ([ARM64_DYNAREC] added some of the new opcodes too)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_0f.c | 5 | ||||
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_660f.c | 32 | ||||
| -rw-r--r-- | src/emu/x64run0f.c | 15 | ||||
| -rw-r--r-- | src/emu/x64run660f.c | 42 | ||||
| -rw-r--r-- | src/tools/my_cpuid.c | 25 |
5 files changed, 115 insertions, 4 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index 058478c6..6d5907f7 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -2468,6 +2468,11 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin IFX(X_CF) { BFIw(xFlags, x3, F_CF, 1); } MOVxw_REG(ed, x1); break; + case 7: + INST_NAME("RDPID Ed"); + GETED(0); + CALL_(helper_getcpu, ed, x2); + break; default: DEFAULT; } else switch((nextop>>3)&7) { diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c index 0f336876..f2184f58 100644 --- a/src/dynarec/arm64/dynarec_arm64_660f.c +++ b/src/dynarec/arm64/dynarec_arm64_660f.c @@ -2455,7 +2455,37 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n emit_shrd16(dyn, ninst, ed, gd, x4, x5, x6); EWBACK; break; - + case 0xAE: + nextop = F8; + if(MODREG) + switch (nextop) { + default: + DEFAULT; + } + else + switch((nextop>>3)&7) { + case 6: + INST_NAME("CLWB Ed"); + MESSAGE(LOG_DUMP, "Need Optimization?\n"); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0); + if(ed!=x1) { + MOVx_REG(x1, ed); + } + CALL_(native_clflush, -1, 0); + break; + case 7: + INST_NAME("CLFLUSHOPT Ed"); + MESSAGE(LOG_DUMP, "Need Optimization?\n"); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0); + if(ed!=x1) { + MOVx_REG(x1, ed); + } + CALL_(native_clflush, -1, 0); + break; + default: + DEFAULT; + } + break; case 0xAF: INST_NAME("IMUL Gw,Ew"); SETFLAGS(X_ALL, SF_SET); diff --git a/src/emu/x64run0f.c b/src/emu/x64run0f.c index 041b8320..911d80b1 100644 --- a/src/emu/x64run0f.c +++ b/src/emu/x64run0f.c @@ -90,6 +90,18 @@ uintptr_t Run0F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step) GETED(0); if(MODREG) switch(nextop) { + case 0xC8: /* MONITOR */ + // this is a privilege opcode... + #ifndef TEST_INTERPRETER + emit_signal(emu, SIGSEGV, (void*)R_RIP, 0); + #endif + break; + case 0xC9: /* MWAIT */ + // this is a privilege opcode... + #ifndef TEST_INTERPRETER + emit_signal(emu, SIGSEGV, (void*)R_RIP, 0); + #endif + break; case 0xD0: if(R_RCX) { #ifndef TEST_INTERPRETER @@ -1803,6 +1815,9 @@ uintptr_t Run0F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step) ED->dword[1] = 1; } break; + case 7: /* RDPID Ed */ + ED->q[0] = helper_getcpu(emu); + break; default: return 0; } diff --git a/src/emu/x64run660f.c b/src/emu/x64run660f.c index 291a3513..6bd25132 100644 --- a/src/emu/x64run660f.c +++ b/src/emu/x64run660f.c @@ -21,6 +21,9 @@ #include "box64context.h" #include "signals.h" #include "bridge.h" +#ifdef DYNAREC +#include "custommem.h" +#endif #include "modrm.h" #include "x64compstrings.h" @@ -699,6 +702,15 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr) GX->ud[1] = 0; break; + case 0x82: /* INVPCID */ + nextop = F8; + GETED(0); + // this is a privilege opcode... + #ifndef TEST_INTERPRETER + emit_signal(emu, SIGSEGV, (void*)R_RIP, 0); + #endif + break; + case 0xDB: /* AESIMC Gx, Ex */ nextop = F8; GETEX(0); @@ -1886,7 +1898,35 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr) else EW->word[0] = shrd16(emu, EW->word[0], GW->word[0], tmp8u); break; - + case 0xAE: /* Grp Ed (SSE) */ + nextop = F8; + if(MODREG) + switch(nextop) { + default: + return 0; + } + else + switch((nextop>>3)&7) { + case 6: /* CLWB Ed */ + // same code and CLFLUSH, is it ok? + _GETED(0); + #if defined(DYNAREC) && !defined(TEST_INTERPRETER) + if(box64_dynarec) + cleanDBFromAddressRange((uintptr_t)ED, 8, 0); + #endif + break; + case 7: /* CLFLUSHOPT Ed */ + // same code and CLFLUSH, is it ok? + _GETED(0); + #if defined(DYNAREC) && !defined(TEST_INTERPRETER) + if(box64_dynarec) + cleanDBFromAddressRange((uintptr_t)ED, 8, 0); + #endif + break; + default: + return 0; + } + break; case 0xAF: /* IMUL Gw,Ew */ nextop = F8; GETEW(0); diff --git a/src/tools/my_cpuid.c b/src/tools/my_cpuid.c index f69656fc..7316937a 100644 --- a/src/tools/my_cpuid.c +++ b/src/tools/my_cpuid.c @@ -268,16 +268,21 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) R_EAX |= cpu<<24; }*/ R_EDX = 1 // fpu + | 1<<1 // vme | 1<<2 // debugging extension | 1<<3 // pse | 1<<4 // rdtsc | 1<<5 // msr | 1<<6 // pae + | 1<<7 // mcheck extension | 1<<8 // cmpxchg8 | 1<<11 // sep (sysenter & sysexit) | 1<<12 // mtrr + | 1<<13 // pgb + | 1<<14 // mcheck arch | 1<<15 // cmov | 1<<16 // pat + | 1<<17 // pse36 | 1<<19 // clflush (seems to be with SSE2) | 1<<21 // DS, used with VMX, is that usefull? | 1<<23 // mmx @@ -288,7 +293,9 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) ; R_ECX = 1<<0 // SSE3 | 1<<1 // PCLMULQDQ - | 1<<5 // VMX //is that usefull + | (box64_cputype?0:1)<<2 // DS 64bits + | 1<<3 // Monitor/MWait (priviledge instructions) + | (box64_cputype?0:1)<<5 // VMX //is that usefull | 1<<9 // SSSE3 | box64_avx2<<12 // fma | 1<<13 // cx16 (cmpxchg16) @@ -302,6 +309,7 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) | box64_avx<<28 // AVX | box64_avx<<29 // F16C | box64_avx2<<30 // RDRAND + | 0<<31 // Hypervisor guest running ; break; case 0x2: @@ -375,13 +383,22 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) R_EBX = box64_avx<<3 | // BMI1 box64_avx2<<5 | //AVX2 + (box64_cputype?0:1)<<6 | // FDP_EXCPTN_ONLY + 1<<7 | // SMEP box64_avx2<<8 | //BMI2 + (box64_cputype?0:1)<<9 | // Enhanced REP MOVSB // is it a good idea? + 1<<10 | //INVPCID (priviledge instruction + (box64_cputype?0:1)<<13 | // Deprecates FPU CS and FPU DS + 0<<18 | // RDSEED box64_avx2<<19 | //ADX + 1<<23 | // CLFLUSHOPT + 1<<24 | // CLWB box64_shaext<<29| // SHA extension 0; R_RCX = box64_avx<<9 | //VAES box64_avx2<<10 | //VPCLMULQDQ. + 1<<22 | // RDPID 0; R_RDX = 0; @@ -523,7 +540,8 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) //| 1<<7 // misaligned SSE | 1<<8 // 3DNowPrefetch //| 1<<10 // IBS - //| 1<<11 // SSE5 + //| 1<<11 // XOP + //| 1<<16 // FMA4 ; R_EDX = 1 // fpu | 1<<2 // debugging extension @@ -534,9 +552,12 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) | 1<<8 // cmpxchg8 | 1<<11 // sep (sysenter & sysexit) | 1<<12 // mtrr + | 1<<13 // pge | 1<<15 // cmov | 1<<16 // pat + | 1<<17 // pse36 | 1<<19 // clflush (seems to be with SSE2) + | 1<<20 // NX | 1<<21 // DS, used with VMX, is that usefull? | 1<<22 // MMXext | 1<<23 // mmx |