Added support for SSE4.1, and added a couple of opcode ([ARM64_DYNAREC] too)

5 files changed, 47 insertions, 2 deletions

diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index 3ae0be77..b54638d7 100755
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -397,6 +397,20 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                     SXTL_32(q0, q1);     // 32bits->64bits

                     break;

 

+                case 0x2B:

+                    INST_NAME("PACKUSDW Gx, Ex");  // SSE4 opcode!

+                    nextop = F8;

+                    GETEX(q1, 0, 0);

+                    GETGX(q0, 1);

+                    v0 = fpu_get_scratch(dyn);

+                    VEORQ(v0, v0, v0);

+                    SMAX_32(v0, v0, q0);    // values < 0 => 0

+                    UQXTN_16(q0, v0);

+                    VEORQ(v0, v0, v0);

+                    SMAX_32(v0, v0, q1);

+                    UQXTN2_16(q0, v0);

+                    break;

+

                 case 0x30:

                     INST_NAME("PMOVZXBW Gx, Ex");  // SSE4 opcode!

                     nextop = F8;

@@ -500,6 +514,13 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                     GETGX(q0, 1);

                     UMAXQ_32(q0, q0, q1);

                     break;

+                case 0x40:

+                    INST_NAME("PMULLD Gx, Ex");  // SSE4 opcode!

+                    nextop = F8;

+                    GETEX(q1, 0, 0);

+                    GETGX(q0, 1);

+                    VUMULL_32(q0, q0, q1);

+                    break;

 

                 case 0xDB:

                     INST_NAME("AESIMC Gx, Ex");  // AES-NI

diff --git a/src/emu/x64run660f.c b/src/emu/x64run660f.c
index 57440997..91f54814 100644
--- a/src/emu/x64run660f.c
+++ b/src/emu/x64run660f.c
@@ -445,6 +445,19 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr)
                     GX->sq[i] = EX->sd[i];

                 break;

             

+            case 0x2B:  /* PACKUSDW Gx, Ex */

+                nextop = F8;

+                GETEX(0);

+                GETGX;

+                for(int i=3; i>=0; --i)

+                    GX->uw[i] = ((GX->sd[i]<0)?0:(GX->sd[i]>65535)?65535:GX->sd[i]);

+                if(GX==EX)

+                    GX->q[1] = GX->q[0];

+                else

+                    for(int i=0; i<4; ++i)

+                        GX->uw[i+4] = ((EX->sd[i]<0)?0:(EX->sd[i]>65535)?65535:EX->sd[i]);

+                break;

+

             case 0x30: /* PMOVZXBW Gx, Ex */

                 nextop = F8;

                 GETEX(0);

@@ -552,6 +565,14 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr)
                     if(GX->ud[i]<EX->ud[i])

                         GX->ud[i] = EX->ud[i];

                 break;

+            case 0x40:  /* PMULLD Gx, Ex */

+                nextop = F8;

+                GETEX(0);

+                GETGX;

+                for(int i=0; i<4; ++i)

+                    if(GX->ud[i]<EX->ud[i])

+                        GX->ud[i] *= EX->ud[i];

+                break;

 

             case 0xDB:  /* AESIMC Gx, Ex */

                 nextop = F8;

diff --git a/src/tools/box64stack.c b/src/tools/box64stack.c
index 42412e29..97623261 100755
--- a/src/tools/box64stack.c
+++ b/src/tools/box64stack.c
@@ -160,7 +160,7 @@ void SetupInitialStack(x64emu_t *emu)
     Push(emu, real_getauxval(14)); Push(emu, 14);       //AT_EGID(14)
     Push(emu, p_x86_64); Push(emu, 15);                 //AT_PLATFORM(15)=&"x86_64"
     // Push HWCAP: same as CPUID 1.EDX
-    Push(emu,   1         // fpu 
+    Push(emu,   1<<0      // fpu 
               | 1<<4      // rdtsc
               | 1<<8      // cmpxchg8
               | 1<<11     // sep (sysenter & sysexit)
@@ -170,6 +170,8 @@ void SetupInitialStack(x64emu_t *emu)
               | 1<<24     // fxsr (fxsave, fxrestore)
               | 1<<25     // SSE
               | 1<<26     // SSE2
+              | 1<<28     // hyper threading
+              | 1<<30     // ia64
         );
     Push(emu, 16);                                      //AT_HWCAP(16)=...
     //Push(emu, sysconf(_SC_CLK_TCK)); Push(emu, 17);     //AT_CLKTCK(17)=times() frequency
diff --git a/src/tools/my_cpuid.c b/src/tools/my_cpuid.c
index 06b725aa..20355462 100644
--- a/src/tools/my_cpuid.c
+++ b/src/tools/my_cpuid.c
@@ -87,6 +87,7 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u)
                     | 1<<9      // SSSE3
                     | 1<<12     // fma
                     | 1<<13     // cx16 (cmpxchg16)
+                    | 1<<19     // SSE4_1
                     | 1<<22     // MOVBE
                     | 1<<25     // aesni
                     ; 
diff --git a/src/wrapped/wrappedlibc.c b/src/wrapped/wrappedlibc.c
index ca4db823..770fdbf8 100755
--- a/src/wrapped/wrappedlibc.c
+++ b/src/wrapped/wrappedlibc.c
@@ -1548,7 +1548,7 @@ void CreateCPUInfoFile(int fd)
         P;
         sprintf(buff, "bogomips\t: %g\n", bogoMips);
         P;
-        sprintf(buff, "flags\t\t: fpu cx8 sep cmov clflush mmx sse sse2 syscall tsc lahf_lm ssse3 ht tm lm fma fxsr cpuid pclmulqdq cx16 aes movbe pni\n");
+        sprintf(buff, "flags\t\t: fpu cx8 sep cmov clflush mmx sse sse2 syscall tsc lahf_lm ssse3 ht tm lm fma fxsr cpuid pclmulqdq cx16 aes movbe pni sse4_1\n");
         P;
         sprintf(buff, "address sizes\t: 46 bits physical, 48 bits virtual\n");
         P;