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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-24 14:37:51 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-24 14:37:51 +0100 |
| commit | 5a8b5c8af4731a5fcfb8c554e2e2d71495f5abfa (patch) | |
| tree | 437b3399603b6fab40683fc86319853c4d711208 /src | |
| parent | 1e3c599b4eef7ea802bcefcb5d24e5dff9f2a603 (diff) | |
| download | box64-5a8b5c8af4731a5fcfb8c554e2e2d71495f5abfa.tar.gz box64-5a8b5c8af4731a5fcfb8c554e2e2d71495f5abfa.zip | |
[DYNAREC] Added 64 C7 opcode
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/arm64_emitter.h | 1 | ||||
| -rw-r--r-- | src/dynarec/dynarec_arm64_64.c | 17 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h index 23e45fad..86fe165f 100755 --- a/src/dynarec/arm64_emitter.h +++ b/src/dynarec/arm64_emitter.h @@ -262,6 +262,7 @@ #define STRw_REG_LSL2(Rt, Rn, Rm) EMIT(STR_REG_gen(0b10, Rm, 0b011, 1, Rn, Rt)) #define STRB_REG(Rt, Rn, Rm) EMIT(STR_REG_gen(0b00, Rm, 0b011, 0, Rn, Rt)) #define STRH_REG(Rt, Rn, Rm) EMIT(STR_REG_gen(0b01, Rm, 0b011, 0, Rn, Rt)) +#define STRxw_REG(Rt, Rn, Rm) EMIT(STR_REG_gen(rex.w?0b11:0b10, Rm, 0b011, 0, Rn, Rt)) // LOAD/STORE PAIR #define MEMPAIR_gen(size, L, op2, imm7, Rt2, Rn, Rt) ((size)<<31 | 0b101<<27 | (op2)<<23 | (L)<<22 | (imm7)<<15 | (Rt2)<<10 | (Rn)<<5 | (Rt)) diff --git a/src/dynarec/dynarec_arm64_64.c b/src/dynarec/dynarec_arm64_64.c index d86be338..434cc2c3 100644 --- a/src/dynarec/dynarec_arm64_64.c +++ b/src/dynarec/dynarec_arm64_64.c @@ -30,6 +30,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin int32_t j32; uint8_t gd, ed; uint8_t wback; + int64_t i64; int fixedaddress; MAYUSE(j32); @@ -69,6 +70,22 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0xC7: + INST_NAME("MOV FS:Ed, Id"); + grab_segdata(dyn, addr, ninst, x4, _FS); + nextop=F8; + if(MODREG) { // reg <= i32 + i64 = F32S; + ed = xRAX+(nextop&7)+(rex.b<<3); + MOV64xw(ed, i64); + } else { // mem <= i32 + addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 4); + i64 = F32S; + MOV64xw(x3, i64); + STRxw_REG(x3, ed, x4); + } + break; + default: DEFAULT; } |