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| author | Haichen Wu <www.wxmqq@gmail.com> | 2024-04-06 16:46:45 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-06 10:46:45 +0200 |
| commit | 5f4f9337cdce67d7dfd437e8c8517c3b50d788f7 (patch) | |
| tree | 98330b5774416ea4b3dc308a524f0914065fb587 /src | |
| parent | 2a75d283867fc7a09b53a3a446989cf1b1b9998d (diff) | |
| download | box64-5f4f9337cdce67d7dfd437e8c8517c3b50d788f7.tar.gz box64-5f4f9337cdce67d7dfd437e8c8517c3b50d788f7.zip | |
[LA64_DYNAREC] Added more SSE/SSE2 instructions (#1421)
* [LA64_DYNAREC] Added more SSE/SSE2 instructions * [LA64_DYNAREC] Added more SSE/SSE2 instructions
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_f20f.c | 35 | ||||
| -rw-r--r-- | src/dynarec/la64/la64_printer.c | 15 |
2 files changed, 50 insertions, 0 deletions
diff --git a/src/dynarec/la64/dynarec_la64_f20f.c b/src/dynarec/la64/dynarec_la64_f20f.c index d8b8cc17..d3d22596 100644 --- a/src/dynarec/la64/dynarec_la64_f20f.c +++ b/src/dynarec/la64/dynarec_la64_f20f.c @@ -62,6 +62,21 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int } VEXTRINS_D(v0, v1, 0); // v0[63:0] = v1[63:0] break; + case 0x11: + INST_NAME("MOVSD Ex, Gx"); + nextop = F8; + GETG; + v0 = sse_get_reg(dyn, ninst, x1, gd, 0); + if(MODREG) { + ed = (nextop&7)+ (rex.b<<3); + d0 = sse_get_reg(dyn, ninst, x1, ed, 0); + FMOV_D(d0, v0); + } else { + addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 1, 0); + FST_D(v0, ed, fixedaddress); + SMWRITE2(); + } + break; case 0x58: INST_NAME("ADDSD Gx, Ex"); nextop = F8; @@ -72,6 +87,16 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int FADD_D(d0, v0, v1); VEXTRINS_D(v0, d0, 0); // v0[63:0] = v1[63:0] break; + case 0x59: + INST_NAME("MULSD Gx, Ex"); + nextop = F8; + // TODO: fastnan handling + GETGX(v0, 1); + GETEXSD(v1, 0); + d0 = fpu_get_scratch(dyn); + FMUL_D(d0, v0, v1); + VEXTRINS_D(v0, d0, 0); // v0[63:0] = v1[63:0] + break; case 0x5C: INST_NAME("SUBSD Gx, Ex"); nextop = F8; @@ -82,6 +107,16 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int FSUB_D(d0, v0, v1); VEXTRINS_D(v0, d0, 0); // v0[63:0] = v1[63:0] break; + case 0x5E: + INST_NAME("DIVSD Gx, Ex"); + nextop = F8; + // TODO: fastnan handling + GETGX(v0, 1); + GETEXSD(v1, 0); + d0 = fpu_get_scratch(dyn); + FDIV_D(d0, v0, v1); + VEXTRINS_D(v0, d0, 0); // v0[63:0] = v1[63:0] + break; default: DEFAULT; } diff --git a/src/dynarec/la64/la64_printer.c b/src/dynarec/la64/la64_printer.c index 02c2db1e..2a45eebd 100644 --- a/src/dynarec/la64/la64_printer.c +++ b/src/dynarec/la64/la64_printer.c @@ -477,6 +477,21 @@ const char* la64_print(uint32_t opcode, uintptr_t addr) snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FSUB.D", fpnames[Rd], fpnames[Rj], fpnames[Rk]); return buff; } + // FMUL.D + if(isMask(opcode, "00000001000001010kkkkkjjjjjddddd", &a)) { + snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FMUL.D", fpnames[Rd], fpnames[Rj], fpnames[Rk]); + return buff; + } + // FDIV.D + if(isMask(opcode, "00000001000001110kkkkkjjjjjddddd", &a)) { + snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FDIV.D", fpnames[Rd], fpnames[Rj], fpnames[Rk]); + return buff; + } + // VEXTRINS.D + if(isMask(opcode, "01110011100000iiiiiiiijjjjjddddd", &a)) { + snprintf(buff, sizeof(buff), "%-15s %s, %s, %d", "VEXTRINS.D", fpnames[Rd], fpnames[Rj], signExtend(imm, 8)); + return buff; + } // VLD if(isMask(opcode, "0010110000iiiiiiiiiiiijjjjjddddd", &a)) { snprintf(buff, sizeof(buff), "%-15s %s, %s, %d", "VLD.D", vrpnames[Rd], Xt[Rj], signExtend(imm, 12)); |