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authorYang Liu <liuyang22@iscas.ac.cn>2025-08-02 18:47:30 +0800
committerGitHub <noreply@github.com>2025-08-02 12:47:30 +0200
commit6221b01976c287e8ce6858eb09309fd70d675b67 (patch)
tree0a108bf635215dce0861324fec963c53e0439421 /src
parentcaac35cc1e9e05275850b154b6d0ebc4a74ca835 (diff)
downloadbox64-6221b01976c287e8ce6858eb09309fd70d675b67.tar.gz
box64-6221b01976c287e8ce6858eb09309fd70d675b67.zip
[RV64_DYNAREC] Fixed scalar and vector versions of mmx PSRAW/PSRAD (#2880)
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/rv64/dynarec_rv64_0f.c4
-rw-r--r--src/dynarec/rv64/dynarec_rv64_0f_vector.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_0f.c b/src/dynarec/rv64/dynarec_rv64_0f.c
index 1ced055c..e9de73cf 100644
--- a/src/dynarec/rv64/dynarec_rv64_0f.c
+++ b/src/dynarec/rv64/dynarec_rv64_0f.c
@@ -2791,7 +2791,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
             nextop = F8;
             GETGM();
             GETEM(x4, 0, 1);
-            LBU(x1, wback, fixedaddress);
+            LD(x1, wback, fixedaddress);
             ADDI(x2, xZR, 15);
             if (cpuext.zbb) {
                 MINU(x1, x1, x2);
@@ -2810,7 +2810,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
             nextop = F8;
             GETGM();
             GETEM(x4, 0, 1);
-            LBU(x1, wback, fixedaddress);
+            LD(x1, wback, fixedaddress);
             ADDI(x2, xZR, 31);
             if (cpuext.zbb) {
                 MINU(x1, x1, x2);
diff --git a/src/dynarec/rv64/dynarec_rv64_0f_vector.c b/src/dynarec/rv64/dynarec_rv64_0f_vector.c
index 65082437..c3e7dfdd 100644
--- a/src/dynarec/rv64/dynarec_rv64_0f_vector.c
+++ b/src/dynarec/rv64/dynarec_rv64_0f_vector.c
@@ -1312,11 +1312,11 @@ uintptr_t dynarec64_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip,
             GETGM_vector(v0);
             SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
             GETEM_vector(v1, 0);
-            SET_ELEMENT_WIDTH(x1, u8, 1);
             MOV32w(x5, i32 - 1);
             q0 = fpu_get_scratch(dyn);
             VMINU_VX(q0, v1, x5, VECTOR_UNMASKED);
             VMV_X_S(x4, q0);
+            SET_ELEMENT_WIDTH(x1, u8, 1);
             VSRA_VX(v0, v0, x4, VECTOR_UNMASKED);
             break;
         case 0xE5: