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authorYang Liu <liuyang22@iscas.ac.cn>2025-05-15 19:00:09 +0800
committerGitHub <noreply@github.com>2025-05-15 13:00:09 +0200
commit649af04fa540ff2d5cb581e2d2f8213be1381fc0 (patch)
treee7d3289106b96b2c0f86e892c49d03499d7fcce7 /src
parent3b97efb9ca982c3641201e8571c09beb0d5d4cb9 (diff)
downloadbox64-649af04fa540ff2d5cb581e2d2f8213be1381fc0.tar.gz
box64-649af04fa540ff2d5cb581e2d2f8213be1381fc0.zip
[RV64_DYNAREC] Added more opcodes for vector (#2637)
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/rv64/dynarec_rv64_0f_vector.c11
-rw-r--r--src/dynarec/rv64/dynarec_rv64_660f_vector.c20
2 files changed, 30 insertions, 1 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_0f_vector.c b/src/dynarec/rv64/dynarec_rv64_0f_vector.c
index 2d15e636..b1569238 100644
--- a/src/dynarec/rv64/dynarec_rv64_0f_vector.c
+++ b/src/dynarec/rv64/dynarec_rv64_0f_vector.c
@@ -477,6 +477,17 @@ uintptr_t dynarec64_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip,
                     vector_vsetvli(dyn, ninst, x1, VECTOR_SEW16, VECTOR_LMUL1, 1);
                     VNSRL_WI(q0, v0, 1, VECTOR_UNMASKED);
                     break;
+                case 0xC8 ... 0xCD:
+                    return 0;
+                default:
+                    DEFAULT_VECTOR;
+            }
+            break;
+        case 0x3A:
+            nextop = F8;
+            switch (nextop) {
+                case 0xCC:
+                    return 0;
                 default:
                     DEFAULT_VECTOR;
             }
diff --git a/src/dynarec/rv64/dynarec_rv64_660f_vector.c b/src/dynarec/rv64/dynarec_rv64_660f_vector.c
index 42a8e449..9f74f0bb 100644
--- a/src/dynarec/rv64/dynarec_rv64_660f_vector.c
+++ b/src/dynarec/rv64/dynarec_rv64_660f_vector.c
@@ -101,6 +101,20 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
                 VMV_S_X(v0, x4);
             }
             break;
+        case 0x13:
+            INST_NAME("MOVLPD Eq, Gx");
+            nextop = F8;
+            SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
+            GETGX_vector(v0, 0, VECTOR_SEW64);
+            if (MODREG) {
+                DEFAULT;
+                return addr;
+            }
+            addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 1, 0);
+            VMV_X_S(x4, v0);
+            SD(x4, ed, fixedaddress);
+            SMWRITE2();
+            break;
         case 0x14:
             INST_NAME("UNPCKLPD Gx, Ex");
             nextop = F8;
@@ -907,6 +921,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
                     GETGX_vector(q0, 1, VECTOR_SEW32);
                     VMUL_VV(q0, q1, q0, VECTOR_UNMASKED);
                     break;
+                case 0xDB ... 0xDF:
+                    return 0;
                 default:
                     DEFAULT_VECTOR;
             }
@@ -1049,7 +1065,9 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
                     VECTOR_LOAD_VMASK((u8 & 0xf), x4, 1);
                     VMERGE_VVM(q0, v1, d0);
                     break;
-                case 0x63: return 0;
+                case 0x44:
+                case 0x63:
+                case 0xDF: return 0;
                 default: DEFAULT_VECTOR;
             }
             break;