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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-10-23 18:32:02 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-10-23 18:32:02 +0200 |
| commit | 65fc95b61421534de54c92907020540dee261b00 (patch) | |
| tree | 8fab4444add4d405445008e78d3b4460b6dd00d6 /src | |
| parent | 4354e8c86120396e9aaa0d917f628958198bb0fd (diff) | |
| download | box64-65fc95b61421534de54c92907020540dee261b00.tar.gz box64-65fc95b61421534de54c92907020540dee261b00.zip | |
[ARM64_DYNAREC] Fixed some cases of 0F D3 opcode
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/arm64_emitter.h | 1 | ||||
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_0f.c | 13 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h index 27a60114..58eac553 100644 --- a/src/dynarec/arm64/arm64_emitter.h +++ b/src/dynarec/arm64/arm64_emitter.h @@ -1769,6 +1769,7 @@ #define MOVI_8(Rd, imm8) EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd)) #define MOVI_16(Rd, imm8) EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b1000, ((imm8)&0b11111), Rd)) #define MOVI_32(Rd, imm8) EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b0000, ((imm8)&0b11111), Rd)) +#define MOVI_64(Rd, imm8) EMIT(MOVI_vector(0, 1, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd)) // SHLL and eXtend Long #define SHLL_vector(Q, U, immh, immb, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b011110<<23 | (immh)<<19 | (immb)<<16 | 0b10100<<11 | 1<<10 | (Rn)<<5 | (Rd)) diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index 440d1fe9..2dc7f064 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -1947,12 +1947,13 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin nextop = F8; GETGM(d0); GETEM(d1, 0); - if(MODREG) - q0 = fpu_get_scratch(dyn); - else - q0 = d1; - NEG_64(q0, d1); - USHL_R_64(d0, d0, q0); + v0 = fpu_get_scratch(dyn); + //MOVI_64(v0, 64); not 64! + MOV32w(x1, 64); + VMOVQDfrom(v0, 0, x1); + UMIN_32(v0, v0, d1); // limit to 0 .. +64 values (will force 32bits upper part to 0) + NEG_64(v0, v0); + USHL_R_64(d0, d0, v0); break; case 0xD4: INST_NAME("PADDQ Gm,Em"); |