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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-31 17:22:23 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-31 17:22:23 +0200 |
| commit | 663ac80fd060342aeb48ac09e057a9468e79a81b (patch) | |
| tree | 86b774c05bf477bf5f793bc08dfc573a6d3c5646 /src | |
| parent | 2d34788607cc84b1821ff19078d6c7b784047a22 (diff) | |
| download | box64-663ac80fd060342aeb48ac09e057a9468e79a81b.tar.gz box64-663ac80fd060342aeb48ac09e057a9468e79a81b.zip | |
[DYNAREC] Added 0F 67/71 opcodes
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/arm64_emitter.h | 2 | ||||
| -rwxr-xr-x | src/dynarec/dynarec_arm64_0f.c | 67 |
2 files changed, 68 insertions, 1 deletions
diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h index 74c4749f..d4666ae9 100755 --- a/src/dynarec/arm64_emitter.h +++ b/src/dynarec/arm64_emitter.h @@ -704,7 +704,7 @@ #define VSHLQ_32(Vd, Vn, shift) EMIT(SHL_vector(1, 0b0100 | (((shift)>>3)&3), (shift)&7, Vn, Vd)) #define VSHLQ_64(Vd, Vn, shift) EMIT(SHL_vector(1, 0b1000 | (((shift)>>3)&7), (shift)&7, Vn, Vd)) #define VSHL_8(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0001, (shift)&7, Vn, Vd)) -#define VSHL_16(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0010 | ((shift)>>3)&1, (shift)&7, Vn, Vd)) +#define VSHL_16(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0010 | (((shift)>>3)&1), (shift)&7, Vn, Vd)) #define VSHL_32(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0100 | (((shift)>>3)&3), (shift)&7, Vn, Vd)) #define SHR_vector(Q, U, immh, immb, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b011110<<23 | (immh)<<19 | (immb)<<16 | 0b00000<<11 | 1<<10 | (Rn)<<5 | (Rd)) diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c index a3432b1b..446b2cb9 100755 --- a/src/dynarec/dynarec_arm64_0f.c +++ b/src/dynarec/dynarec_arm64_0f.c @@ -436,6 +436,22 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin VZIP1_32(d0, d0, d1); break; + case 0x67: + INST_NAME("PACKUSWB Gm, Em"); + nextop = F8; + GETGM(v0); + q0 = fpu_get_scratch(dyn); + VMOVeD(q0, 0, v0, 0); + if(MODREG) { + v1 = mmx_get_reg(dyn, ninst, x1, (nextop&7)); + VMOVeD(q0, 1, v1, 0); + } else { + addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0); + VLD1_64(q0, 1, ed); + } + SQXTUN_8(v0, q0); + break; + case 0x6E: INST_NAME("MOVD Gm, Ed"); nextop = F8; @@ -464,6 +480,57 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0x71: + nextop = F8; + switch((nextop>>3)&7) { + case 2: + INST_NAME("PSRLW Em, Ib"); + GETEM(q0, 1); + u8 = F8; + if(u8) { + if (u8>15) { + VEOR(q0, q0, q0); + } else if(u8) { + VSHR_16(q0, q0, u8); + } + if(!MODREG) { + VSTR64_U12(q0, ed, fixedaddress); + } + } + break; + case 4: + INST_NAME("PSRAW Ex, Ib"); + GETEM(q0, 1); + u8 = F8; + if(u8>15) u8=15; + if(u8) { + VSSHR_16(q0, q0, u8); + } + if(!MODREG) { + VSTR64_U12(q0, ed, fixedaddress); + } + break; + case 6: + INST_NAME("PSLLW Ex, Ib"); + GETEM(q0, 1); + u8 = F8; + if(u8) { + if (u8>15) { + VEOR(q0, q0, q0); + } else { + VSHL_16(q0, q0, u8); + } + if(!MODREG) { + VSTR64_U12(q0, ed, fixedaddress); + } + } + break; + default: + *ok = 0; + DEFAULT; + } + break; + #define GO(GETFLAGS, NO, YES, F) \ READFLAGS(F); \ i32_ = F32S; \ |