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| author | ptitSeb <sebastien.chev@gmail.com> | 2024-04-12 18:14:44 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2024-04-12 18:14:51 +0200 |
| commit | 6ce570f4a514797aafe4c02bb750106365b5a3e7 (patch) | |
| tree | 7e53320fb2f0c83d32e8ed4cdf7a14f454807b89 /src | |
| parent | b95b99b3c9aa7cdda09684c672178988fbe4730b (diff) | |
| download | box64-6ce570f4a514797aafe4c02bb750106365b5a3e7.tar.gz box64-6ce570f4a514797aafe4c02bb750106365b5a3e7.zip | |
Revert some cpuid changes, they are more wrong then right it seems
Diffstat (limited to 'src')
| -rw-r--r-- | src/tools/my_cpuid.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/tools/my_cpuid.c b/src/tools/my_cpuid.c index 7cf04ffa..46dbab76 100644 --- a/src/tools/my_cpuid.c +++ b/src/tools/my_cpuid.c @@ -224,7 +224,7 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) switch(tmp32u) { case 0x0: // emulate a P4. TODO: Emulate a Core2? - R_EAX = 0x00000015;//0x80000004; + R_EAX = 0x0000000f;//was 0x15 before, but something seems wrong for leaf 0x15, and cpu-z take that as pure cpu speed... // return GenuineIntel R_EBX = 0x756E6547; R_EDX = 0x49656E69; @@ -390,7 +390,7 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u) break; case 0x80000000: // max extended - R_EAX = 0x80000007; + R_EAX = 0x80000005; // was 0x80000007 before, but L2 cache description 0x80000006 is not correct and make some AC games to assert about l2 cache value coherency... break; case 0x80000001: //Extended Processor Signature and Feature Bits R_EAX = 0; // reserved |