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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-04-03 10:00:52 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-04-03 10:00:52 +0200 |
| commit | 717c0e1299a84dac2914e8eeaf00b47ca2a9cf8f (patch) | |
| tree | 2354a8db737c944283740402380ed432b51d5f74 /src | |
| parent | 8760064ddb7dedeb2a43fb095d3446328e14c7e2 (diff) | |
| download | box64-717c0e1299a84dac2914e8eeaf00b47ca2a9cf8f.tar.gz box64-717c0e1299a84dac2914e8eeaf00b47ca2a9cf8f.zip | |
[DYNAREC] Added F3 0F E6 opcode
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/dynarec_arm64_f30f.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c index 76042b33..6b395fe2 100755 --- a/src/dynarec/dynarec_arm64_f30f.c +++ b/src/dynarec/dynarec_arm64_f30f.c @@ -344,6 +344,16 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n VMOVQSfrom(v0, 0, x2); break; + case 0xE6: + INST_NAME("CVTDQ2PD Gx, Ex"); + nextop = F8; + GETEX(v1, 0); + GETGX_empty(v0); + d0 = fpu_get_scratch(dyn); + SXTL_32(v0, v1); + SCVTQFD(v0, v0); // there is only I64 -> Double vector conversion, not from i32 + break; + default: DEFAULT; } |