diff options
| author | ptitSeb <sebastien.chev@gmail.com> | 2023-07-23 13:03:46 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-07-23 13:03:46 +0200 |
| commit | 784cc3ba9cf4ea807cb91de68d43b9b855c1993e (patch) | |
| tree | 9287df7fc8e784f5f5da69b80053e4331c583785 /src | |
| parent | 1d5a88a3198c59c5ad27e5ecdcb2f8ef4f712264 (diff) | |
| download | box64-784cc3ba9cf4ea807cb91de68d43b9b855c1993e.tar.gz box64-784cc3ba9cf4ea807cb91de68d43b9b855c1993e.zip | |
[32BITS] Added C4 and C5 opcodes
Diffstat (limited to 'src')
| -rw-r--r-- | src/emu/x64run.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/src/emu/x64run.c b/src/emu/x64run.c index c0e38a8b..b8979e96 100644 --- a/src/emu/x64run.c +++ b/src/emu/x64run.c @@ -1315,7 +1315,32 @@ x64emurun: addr = rex.is32bits?Pop32(emu):Pop64(emu); STEP2 break; - + case 0xC4: /* LES Gd,Ed */ + if(rex.is32bits) { + nextop = F8; + GETED(0); + GETGD; + emu->segs[_ES] = *(__uint16_t*)(((char*)ED)+4); + emu->segs_serial[_ES] = 0; + GD->dword[0] = *(uint32_t*)ED; + } else { + // AVX not supported yet + emit_signal(emu, SIGILL, R_RIP, 0); + } + break; + case 0xC5: /* LDS Gd,Ed */ + if(rex.is32bits) { + nextop = F8; + GETED(0); + GETGD; + emu->segs[_DS] = *(__uint16_t*)(((char*)ED)+4); + emu->segs_serial[_DS] = 0; + GD->dword[0] = *(uint32_t*)ED; + } else { + // AVX not supported yet + emit_signal(emu, SIGILL, R_RIP, 0); + } + break; case 0xC6: /* MOV Eb,Ib */ nextop = F8; GETEB(1); |