[DYNAREC] Added 66 FF INC/DEC opcodes

3 files changed, 108 insertions, 91 deletions

diff --git a/src/dynarec/dynarec_arm64_66.c b/src/dynarec/dynarec_arm64_66.c
index 2722dbc6..680d822d 100755
--- a/src/dynarec/dynarec_arm64_66.c
+++ b/src/dynarec/dynarec_arm64_66.c
@@ -222,6 +222,27 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             }

             break;

             

+        case 0xFF:

+            nextop = F8;

+            switch((nextop>>3)&7) {

+                case 0:

+                    INST_NAME("INC Ew");

+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);

+                    GETEW(x1, 0);

+                    emit_inc16(dyn, ninst, x1, x2, x4);

+                    EWBACK;

+                    break;

+                case 1:

+                    INST_NAME("DEC Ew");

+                    SETFLAGS(X_ALL&~X_CF, SF_SET);

+                    GETEW(x1, 0);

+                    emit_dec16(dyn, ninst, x1, x2, x4);

+                    EWBACK;

+                    break;

+                default:

+                    DEFAULT;

+            }

+            break;

         default:

             DEFAULT;

     }

diff --git a/src/dynarec/dynarec_arm64_emit_math.c b/src/dynarec/dynarec_arm64_emit_math.c
index 91fb0a14..b043ded9 100755
--- a/src/dynarec/dynarec_arm64_emit_math.c
+++ b/src/dynarec/dynarec_arm64_emit_math.c
@@ -833,51 +833,49 @@ void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
 //}
 
 // emit INC16 instruction, from s1 , store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
-//void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
-//{
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        SET_DF(s3, d_inc16);
-//    } else IFX(X_ZF|X_OF|X_AF|X_SF|X_PF) {
-//        SET_DFNONE(s3);
-//    }
-//    IFX(X_AF | X_OF) {
-//        MOV_REG(s4, s1);
-//    }
-//    ADD_IMM8(s1, s1, 1);
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_AF|X_OF) {
-//        ORR_IMM8(s3, s4, 1, 0);     // s3 = op1 | op2
-//        AND_IMM8(s4, s4, 1);        // s4 = op1 & op2
-//
-//        BIC_REG_LSL_IMM5(s3, s3, s1, 0);   // s3 = (op1 | op2) & ~ res
-//        ORR_REG_LSL_IMM5(s3, s3, s4, 0);   // s3 = (op1 & op2) | ((op1 | op2) & ~ res)
-//        IFX(X_AF) {
-//            MOV_REG_LSR_IMM5(s4, s3, 3);
-//            BFI(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
-//        }
-//        IFX(X_OF) {
-//            MOV_REG_LSR_IMM5(s4, s3, 14);
-//            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
-//            BFI(xFlags, s4, F_OF, 1);    // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1
-//        }
-//    }
-//    IFX(X_ZF) {
-//        UXTH(s1, s1, 0);
-//        TSTS_REG_LSL_IMM5(s1, s1, 0);
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 15);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
+        SET_DF(s3, d_inc16);
+    } else IFX(X_ZF|X_OF|X_AF|X_SF|X_PF) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_AF | X_OF) {
+        MOVw_REG(s4, s1);
+    }
+    ADDw_U12(s1, s1, 1);
+    IFX(X_PEND) {
+        STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_AF|X_OF) {
+        ORRw_mask(s3, s4, 0, 0);    // s3 = op1 | op2
+        ANDw_mask(s4, s4, 0, 0);    // s4 = op1 & op2
+        BICw_REG(s3, s3, s1);       // s3 = (op1 | op2) & ~ res
+        ORRw_REG(s3, s3, s4);       // s3 = (op1 & op2) | ((op1 | op2) & ~ res)
+        IFX(X_AF) {
+            LSRw(s4, s3, 3);
+            BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+        IFX(X_OF) {
+            LSRw(s4, s3, 14);
+            EORw_REG_LSR(s4, s4, s4, 1);
+            BFIw(xFlags, s4, F_OF, 1);    // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1
+        }
+    }
+    IFX(X_ZF) {
+        TSTw_mask(s1, 0, 0b001111); // mask=0xffff
+        CSETw(s3, cEQ);
+        BFIw(xFlags, s3, F_ZF, 1);
+    }
+    IFX(X_SF) {
+        LSRw(s3, s1, 15);
+        BFIw(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s3, s4);
+    }
+}
 
 // emit DEC32 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4)
@@ -979,50 +977,48 @@ void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
 //}
 
 // emit DEC16 instruction, from s1, store result in s1 using s3 and s4 as scratch
-//void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
-//{
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        SET_DF(s3, d_dec16);
-//    } else IFX(X_ZF|X_OF|X_AF|X_SF|X_PF) {
-//        SET_DFNONE(s3);
-//    }
-//    IFX(X_AF|X_OF) {
-//        MVN_REG_LSL_IMM5(s4, s1, 0);
-//    }
-//    SUB_IMM8(s1, s1, 1);
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_AF|X_OF) {
-//        ORR_IMM8(s3, s4, 1, 0);     // s3 = ~op1 | op2
-//        AND_IMM8(s4, s4, 1);        // s4 = ~op1 & op2
-//        AND_REG_LSL_IMM5(s3, s3, s1, 0);   // s3 = (~op1 | op2) & res
-//        ORR_REG_LSL_IMM5(s3, s3, s4, 0);   // s3 = (~op1 & op2) | ((~op1 | op2) & res)
-//        IFX(X_AF) {
-//            MOV_REG_LSR_IMM5(s4, s3, 3);
-//            BFI(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
-//        }
-//        IFX(X_OF) {
-//            MOV_REG_LSR_IMM5(s4, s3, 14);
-//            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
-//            BFI(xFlags, s4, F_OF, 1);    // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1
-//        }
-//    }
-//    IFX(X_ZF) {
-//        UXTH(s1, s1, 0);
-//        TSTS_REG_LSL_IMM5(s1, s1, 0);
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 15);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
+        SET_DF(s3, d_dec16);
+    } else IFX(X_ZF|X_OF|X_AF|X_SF|X_PF) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_AF|X_OF) {
+        MVNw_REG(s4, s1);
+    }
+    SUBSw_U12(s1, s1, 1);
+    IFX(X_PEND) {
+        STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_AF|X_OF) {
+        ORRw_mask(s3, s4, 0, 0);    // s3 = ~op1 | op2
+        ANDw_mask(s4, s4, 0, 0);    // s4 = ~op1 & op2
+        ANDw_REG(s3, s3, s1);       // s3 = (~op1 | op2) & res
+        ORRw_REG(s3, s3, s4);       // s3 = (~op1 & op2) | ((~op1 | op2) & res)
+        IFX(X_AF) {
+            LSRw(s4, s3, 3);
+            BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+        IFX(X_OF) {
+            LSRw(s4, s3, 14);
+            EORw_REG_LSR(s4, s4, s4, 1);
+            BFIw(xFlags, s4, F_OF, 1);    // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1
+        }
+    }
+    IFX(X_ZF) {
+        CSETw(s3, cEQ);
+        BFIw(xFlags, s3, F_ZF, 1);
+    }
+    IFX(X_SF) {
+        LSRw(s3, s1, 15);
+        BFIw(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s3, s4);
+    }
+}
 
 // emit ADC32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
 //void emit_adc32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
diff --git a/src/dynarec/dynarec_arm64_helper.h b/src/dynarec/dynarec_arm64_helper.h
index 0a11e94c..04fec1c6 100755
--- a/src/dynarec/dynarec_arm64_helper.h
+++ b/src/dynarec/dynarec_arm64_helper.h
@@ -671,10 +671,10 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
 //void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
 //void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
 void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4);
-//void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
 //void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
 void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4);
-//void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
 //void emit_dec8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
 //void emit_adc32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
 //void emit_adc32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);