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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-11-20 02:59:43 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-19 19:59:43 +0100 |
| commit | 81e4e26dc51b85720fbc3ba2ffe68030e5d227fa (patch) | |
| tree | cc6b62f68664f88fafccad7517a463ea55b56735 /src | |
| parent | 4f6a66f9c60f20c97059215d076effc3c9fafd7f (diff) | |
| download | box64-81e4e26dc51b85720fbc3ba2ffe68030e5d227fa.tar.gz box64-81e4e26dc51b85720fbc3ba2ffe68030e5d227fa.zip | |
[ARM64_DYNAREC] Re-enable weakbarrier for dmb.ishst (#2048)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_helper.h | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h index e76aac02..15a2d423 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.h +++ b/src/dynarec/arm64/dynarec_arm64_helper.h @@ -60,7 +60,7 @@ */ #define STRONGMEM_SIMD_WRITE 2 // The level of SIMD memory writes will be tracked -#define STRONGMEM_LAST_WRITE 2 // The level of a barrier before the last guest memory store will be put +#define STRONGMEM_LAST_WRITE 1 // The level of a barrier before the last guest memory store will be put #define STRONGMEM_SEQ_WRITE 3 // The level of a barrier at every third memory store will be put #if STEP == 1 @@ -165,10 +165,16 @@ do { \ if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) { \ /* Will write but never written, this is the start of a SEQ, put a barrier. */ \ - DMB_ISH(); \ + if (box64_dynarec_weakbarrier) \ + DMB_ISHST(); \ + else \ + DMB_ISH(); \ } else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && dyn->insts[ninst].last_write) { \ /* Last write, put a barrier */ \ - DMB_ISH(); \ + if (box64_dynarec_weakbarrier) \ + DMB_ISHST(); \ + else \ + DMB_ISH(); \ } \ } while (0) @@ -198,7 +204,10 @@ --i; \ if (i >= 0) { \ /* It's a SEQ, put a barrier here. */ \ - DMB_ISH(); \ + if (box64_dynarec_weakbarrier) \ + DMB_ISHST(); \ + else \ + DMB_ISH(); \ } \ } \ dyn->smwrite = 0; \ |