[DYNAREC] Small change to unused PRECISE_CVT part

5 files changed, 19 insertions, 10 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index b06aa319..b69ef087 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -194,6 +194,10 @@
 #define SBCSw_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(0, 1, 1, Rm, Rn, Rd))
 #define SBCSxw_REG(Rd, Rn, Rm)      EMIT(ADDSUBC_gen(rex.w, 1, 1, Rm, Rn, Rd))
 
+// ADR
+#define ADR_gen(immlo, immhi, Rd)   ((immlo)<<29 | 0b10000<<24 | (immhi)<<5 | (Rd))
+#define ADR_S20(Rd, imm)            EMIT(ADR_gen((imm)&3, ((imm)>>2)&0x7ffff, (Rd))
+
 // LDR
 #define LDR_gen(size, op1, imm9, op2, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b01<<22 | (imm9)<<12 | (op2)<<10 | (Rn)<<5 | (Rt))
 #define LDRx_S9_postindex(Rt, Rn, imm9)   EMIT(LDR_gen(0b11, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
diff --git a/src/dynarec/arm64_printer.c b/src/dynarec/arm64_printer.c
index 7849db23..b07d40a4 100755
--- a/src/dynarec/arm64_printer.c
+++ b/src/dynarec/arm64_printer.c
@@ -930,6 +930,12 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         return buff;

     }

 

+    // ADR

+    if(isMask(opcode, "0ss10000iiiiiiiiiiiiiiiiiiiddddd", &a)) {

+      snprintf(buff, sizeof(buff), "ADR, %s, %ld", Xt[Rd], signExtend((imm)<<2|(imms), 20));

+      return buff;

+    }

+

     // LDR / STR

     if(isMask(opcode, "ss111101cciiiiiiiiiiiinnnnnttttt", &a)) {

         char s = '?';

@@ -1344,4 +1350,4 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
 

     snprintf(buff, sizeof(buff), "%08X ???", __builtin_bswap32(opcode));

     return buff;

-}
\ No newline at end of file
+}

diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index b1640609..fd0fd355 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -662,11 +662,11 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr));

             UBFXx(x1, x1, 13, 2);   // extract round requested

             LSLx_REG(x1, x1, 3);

-            ADDx_U12(x1, x1, 8);    // add the actual add+jump opcodes

             // Construct a "switch case", with each case 2 instructions, so 8 bytes

-            BL(+4); // Branch with Link to next, so LR gets next PC address

+            ADR(xLR, GETMARK);

             ADDx_REG(xLR, xLR, x1);

-            B(xLR); // could use RET, but it's not really one

+            B(xLR);

+            MARK;

             VFCVTNSQS(v0, v1);  // 0: Nearest (even)

             B_NEXT_nocond;

             VFCVTMSQS(v0, v1);  // 1: Toward -inf

diff --git a/src/dynarec/dynarec_arm64_f20f.c b/src/dynarec/dynarec_arm64_f20f.c
index e179b2ac..8f458e3d 100755
--- a/src/dynarec/dynarec_arm64_f20f.c
+++ b/src/dynarec/dynarec_arm64_f20f.c
@@ -142,11 +142,11 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr));

             UBFXx(x1, x1, 13, 2);   // extract round requested

             LSLx_REG(x1, x1, 3);

-            ADDx_U12(x1, x1, 8);    // add the actual add+jump opcodes

             // Construct a "switch case", with each case 2 instructions, so 8 bytes

-            BL(+4); // Branch with Link to next, so LR gets next PC address

+            ADR(xLR, GETMARK);

             ADDx_REG(xLR, xLR, x1);

-            B(xLR); // could use RET, but it's not really one

+            B(xLR);

+            MARK;

             FCVTNSxwD(gd, q0);  // 0: Nearest (even)

             B_NEXT_nocond;

             FCVTMSxwD(gd, q0);  // 1: Toward -inf

diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c
index d47a99c5..b4413a60 100755
--- a/src/dynarec/dynarec_arm64_f30f.c
+++ b/src/dynarec/dynarec_arm64_f30f.c
@@ -156,11 +156,10 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr));

             UBFXx(x1, x1, 13, 2);   // extract round requested

             LSLx_REG(x1, x1, 3);

-            ADDx_U12(x1, x1, 8);    // add the actual add+jump opcodes

             // Construct a "switch case", with each case 2 instructions, so 8 bytes

-            BL(+4); // Branch with Link to next, so LR gets next PC address

+            ADR(xLR, GETMARK);

             ADDx_REG(xLR, xLR, x1);

-            B(xLR); // could use RET, but it's not really one

+            B(xLR);

             FCVTNSxwS(gd, q0);  // 0: Nearest (even)

             B_NEXT_nocond;

             FCVTMSxwS(gd, q0);  // 1: Toward -inf