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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-10-30 23:51:55 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-30 16:51:55 +0100 |
| commit | 93cbf59e9e40672b228faf3de77b58917ca0a7e1 (patch) | |
| tree | 0759ea04b8ab5aa54c2849f7463631a950e6aaee /src | |
| parent | e8f97967526effd8b8c034c0975452d80c0e5c65 (diff) | |
| download | box64-93cbf59e9e40672b228faf3de77b58917ca0a7e1.tar.gz box64-93cbf59e9e40672b228faf3de77b58917ca0a7e1.zip | |
[Rv64_DYNAREC] Added more opcodes for vector (#1982)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_660f_vector.c | 22 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_f30f_vector.c | 17 |
2 files changed, 39 insertions, 0 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_660f_vector.c b/src/dynarec/rv64/dynarec_rv64_660f_vector.c index 56177200..28a3b7fd 100644 --- a/src/dynarec/rv64/dynarec_rv64_660f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_660f_vector.c @@ -1802,6 +1802,28 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i GETEX_vector(q1, 0, 0, VECTOR_SEW16); VMULH_VV(q0, q0, q1, VECTOR_UNMASKED); break; + case 0xE6: + if (!box64_dynarec_fastround) return 0; + INST_NAME("CVTTPD2DQ Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1); + GETEX_vector(v1, 0, 0, VECTOR_SEW32); + GETGX_empty_vector(v0); + d0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2); + VMV_V_V(d0, v1); + if (rv64_xtheadvector) { + vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL1, 0.5); + ADDI(x4, xZR, 1); // RTZ + FSRM(x4, x4); + VFNCVT_X_F_W(v0, d0, VECTOR_UNMASKED); + FSRM(xZR, x4); + } else { + VXOR_VV(v0, v0, v0, VECTOR_UNMASKED); + vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL1, 0.5); + VFNCVT_RTZ_X_F_W(v0, d0, VECTOR_UNMASKED); + } + vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL1, 1); + break; case 0xE8: INST_NAME("PSUBSB Gx, Ex"); nextop = F8; diff --git a/src/dynarec/rv64/dynarec_rv64_f30f_vector.c b/src/dynarec/rv64/dynarec_rv64_f30f_vector.c index 4e7f12d2..56a91575 100644 --- a/src/dynarec/rv64/dynarec_rv64_f30f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_f30f_vector.c @@ -490,6 +490,23 @@ uintptr_t dynarec64_F30F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i if (!rv64_xtheadvector) VXOR_VV(v0, v0, v0, VECTOR_UNMASKED); VMV_S_X(v0, x4); break; + case 0x7F: + INST_NAME("MOVDQU Ex, Gx"); + nextop = F8; + if (MODREG) { + SET_ELEMENT_WIDTH(x1, VECTOR_SEWANY, 1); + GETGX_vector(v0, 0, dyn->vector_eew); + ed = (nextop & 7) + (rex.b << 3); + v1 = sse_get_reg_empty_vector(dyn, ninst, x1, ed); + VMV_V_V(v1, v0); + } else { + SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1); // unaligned! + GETGX_vector(v0, 0, dyn->vector_eew); + addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 0, 0); + VSE_V(v0, ed, dyn->vector_eew, VECTOR_UNMASKED, VECTOR_NFIELD1); + SMWRITE2(); + } + break; case 0xAE: case 0xB8: case 0xBC: |