diff options
| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-09-10 16:52:04 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-10 10:52:04 +0200 |
| commit | b0ec124329038418c1401f61b630f588f48f0d2d (patch) | |
| tree | 1f4c3bfa28eb61af674f276eb4f0aaf4d49b717e /src | |
| parent | b40121c9b0334f5ab65de47bb29cd77ec55addef (diff) | |
| download | box64-b0ec124329038418c1401f61b630f588f48f0d2d.tar.gz box64-b0ec124329038418c1401f61b630f588f48f0d2d.zip | |
[RV64_DYNAREC] Added 66 0F D4 PADDQ opcode for vector and fixes SEW cache transform (#1812)
* [RV64_DYNAREC] Added 66 0F D4 PADDQ opcode for vector * [RV64_DYNAREC] Transform SEW cache after fpu cache
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_660f_vector.c | 8 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_helper.c | 7 |
2 files changed, 12 insertions, 3 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_660f_vector.c b/src/dynarec/rv64/dynarec_rv64_660f_vector.c index 3155dfda..08842f23 100644 --- a/src/dynarec/rv64/dynarec_rv64_660f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_660f_vector.c @@ -194,6 +194,14 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i VXOR_VV(q0, q0, q1, VECTOR_UNMASKED); } break; + case 0xD4: + INST_NAME("PADDQ Gx,Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + GETGX_vector(q0, 1, VECTOR_SEW64); + GETEX_vector(q1, 0, 0, VECTOR_SEW64); + VADD_VV(q0, q0, q1, VECTOR_UNMASKED); + break; default: DEFAULT_VECTOR; } diff --git a/src/dynarec/rv64/dynarec_rv64_helper.c b/src/dynarec/rv64/dynarec_rv64_helper.c index 0585b98e..1206004c 100644 --- a/src/dynarec/rv64/dynarec_rv64_helper.c +++ b/src/dynarec/rv64/dynarec_rv64_helper.c @@ -2437,13 +2437,14 @@ static void sewTransform(dynarec_rv64_t* dyn, int ninst, int s1) vector_vsetvl_emul1(dyn, ninst, s1, dyn->insts[jmp].vector_sew); } -void CacheTransform(dynarec_rv64_t* dyn, int ninst, int cacheupd, int s1, int s2, int s3) { - if (cacheupd & 4) - sewTransform(dyn, ninst, s1); +void CacheTransform(dynarec_rv64_t* dyn, int ninst, int cacheupd, int s1, int s2, int s3) +{ if (cacheupd & 2) fpuCacheTransform(dyn, ninst, s1, s2, s3); if (cacheupd & 1) flagsCacheTransform(dyn, ninst, s1); + if (cacheupd & 4) + sewTransform(dyn, ninst, s1); } |