[DYNAREC] Added 0F 5A opcode

3 files changed, 29 insertions, 0 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index 0c75ab5c..8bef590d 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -859,6 +859,18 @@
 #define FCVT_D_S(Dd, Sn)            EMIT(FCVT_precision(0b00, 0b01, Sn, Dd))
 #define FCVT_S_D(Sd, Dn)            EMIT(FCVT_precision(0b01, 0b00, Dn, Sd))
 
+#define FCVTXN_gen(Q, sz, Rn, Rd)   ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10110<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Convert Vn from 2*Double to lower Vd as 2*float
+#define FCVTXN(Vd, Vn)              EMIT(FCVTXN_gen(0, 1, Vn, Vd))
+// Convert Vn from 2*Double to higher Vd as 2*float
+#define FCVTXN2(Vd, Vn)             EMIT(FCVTXN_gen(1, 1, Vn, Vd))
+
+#define FCVTL_gen(Q, sz, Rn, Rd)    ((Q)<<30 | 0<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10111<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Convert lower Vn from 2*float to Vd as 2*double
+#define FCVTL(Vd, Vn)               EMIT(FCVTL_gen(0, 1, Vn, Vd))
+// Convert lower Vn from 2*float to Vd as 2*double
+#define FCVTL2(Vd, Vn)              EMIT(FCVTL_gen(1, 1, Vn, Vd))
+
 #define SCVTF_scalar(sf, type, rmode, opcode, Rn, Rd)   ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (rmode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
 #define SCVTSw(Sd, Wn)              EMIT(SCVTF_scalar(0, 0b00, 0b00, 0b010, Wn, Sd))
 #define SCVTDw(Dd, Wn)              EMIT(SCVTF_scalar(0, 0b00, 0b01, 0b010, Wn, Dd))
diff --git a/src/dynarec/arm64_printer.c b/src/dynarec/arm64_printer.c
index 0f894ea7..67774dd9 100755
--- a/src/dynarec/arm64_printer.c
+++ b/src/dynarec/arm64_printer.c
@@ -971,6 +971,14 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "FCVT S%d, D%d", Rd, Rn);

         return buff;

     }

+    if(isMask(opcode, "0Q00111001100001011110nnnnnddddd", &a)) {

+        snprintf(buff, sizeof(buff), "FCVTL%s V%d.2D, V%d.%dS", a.Q?"2":"", Rd, Rn, a.Q?4:0);

+        return buff;

+    }

+    if(isMask(opcode, "0Q10111000100001011010nnnnnddddd", &a)) {

+        snprintf(buff, sizeof(buff), "FCVTXN%s V%d.%sS, V%d.2D", a.Q?"2":"", Rd, a.Q?4:2, Rn);

+        return buff;

+    }

 

     // FMOV

     if(isMask(opcode, "00011110pp100000010000nnnnnddddd", &a)) {

diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c
index 9f10448a..d060818a 100755
--- a/src/dynarec/dynarec_arm64_0f.c
+++ b/src/dynarec/dynarec_arm64_0f.c
@@ -243,6 +243,15 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             VEORQ(v0, v0, q0);

             break;

 

+        case 0x5A:

+            INST_NAME("CVTPS2PD Gx, Ex");

+            nextop = F8;

+            GETEX(q0, 0);

+            GETGX(q1);

+            d0 = fpu_get_scratch(dyn);

+            FCVTL(q1, q0);

+            break;

+

         #define GO(GETFLAGS, NO, YES, F)   \

             READFLAGS(F);   \

             i32_ = F32S;    \