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authorptitSeb <sebastien.chev@gmail.com>2025-02-20 13:29:50 +0100
committerptitSeb <sebastien.chev@gmail.com>2025-02-20 13:29:50 +0100
commitb7e4cc4f50a8aac75ba9ea2faddcb29e1394612c (patch)
treea89a21fc1bc2025a6fc998481564c19bad34cf12 /src
parenta4908f14076988fe68c934ea2c72601da2705adf (diff)
downloadbox64-b7e4cc4f50a8aac75ba9ea2faddcb29e1394612c.tar.gz
box64-b7e4cc4f50a8aac75ba9ea2faddcb29e1394612c.zip
[ARM64_DYNAREC] Fixed a typo in flag computation for PCMPESTRI and BZHI opcodes
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_660f.c2
-rw-r--r--src/dynarec/arm64/dynarec_arm64_avx_0f38.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index 3c673a36..068dcc8c 100644
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -1454,7 +1454,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                                     CSETw(x5, cLT);

                                     BFIw(xFlags, x5, F_ZF, 1);

                                 }

-                                IFX(F_SF) {

+                                IFX(X_SF) {

                                     CMPSw_REG(x2, x4);

                                     CSETw(x5, cLT);

                                     BFIw(xFlags, x5, F_SF, 1);

diff --git a/src/dynarec/arm64/dynarec_arm64_avx_0f38.c b/src/dynarec/arm64/dynarec_arm64_avx_0f38.c
index c5a9baf5..7ff15039 100644
--- a/src/dynarec/arm64/dynarec_arm64_avx_0f38.c
+++ b/src/dynarec/arm64/dynarec_arm64_avx_0f38.c
@@ -228,7 +228,7 @@ uintptr_t dynarec64_AVX_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, i
             UXTBw(x1, vd);
             CMPSw_U12(x1, rex.w?64:32);
             CSETMxw(x2, cPL);
-            IFX(F_CF) {
+            IFX(X_CF) {
                 BFIw(xFlags, x2, F_CF, 1);
             }
             MVNxw_REG(x2, x2); //prepare mask