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authorptitSeb <sebastien.chev@gmail.com>2021-07-05 22:18:23 +0200
committerptitSeb <sebastien.chev@gmail.com>2021-07-05 22:18:23 +0200
commitb9f38bcefd8b9e913ddad4be87779444d637365d (patch)
treec1f03c941aeb0a25db3112454ba434f2bdb00b9f /src
parent81b1f61aec5b53716bff493b6dc21c6b7ec86df9 (diff)
downloadbox64-b9f38bcefd8b9e913ddad4be87779444d637365d.tar.gz
box64-b9f38bcefd8b9e913ddad4be87779444d637365d.zip
[DYNAREC] Added 66 0F C2 opcode (for CB15)
Diffstat (limited to 'src')
-rwxr-xr-xsrc/dynarec/dynarec_arm64_660f.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index 4c65400b..e1002050 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -1200,6 +1200,38 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             BFIx(gd, x1, 0, 16);

             break;

 

+        case 0xC2:

+            INST_NAME("CMPPD Gx, Ex, Ib");

+            nextop = F8;

+            GETGX(v0);

+            GETEX(v1, 1);

+            u8 = F8;

+            switch(u8&7) {

+                // the inversion of the params in the comparison is there to handle NaN the same way SSE does

+                case 0: FCMEQQD(v0, v0, v1); break;   // Equal

+                case 1: FCMGTQD(v0, v1, v0); break;   // Less than

+                case 2: FCMGEQD(v0, v1, v0); break;   // Less or equal

+                case 3: FCMEQQD(v0, v0, v0); 

+                        if(v0!=v1) {

+                            q0 = fpu_get_scratch(dyn); 

+                            FCMEQQD(q0, v1, v1); 

+                            VANDQ(v0, v0, q0);

+                        }

+                        VMVNQ(v0, v0); 

+                        break;   // NaN (NaN is not equal to himself)

+                case 4: FCMEQQD(v0, v0, v1); VMVNQ(v0, v0); break;   // Not Equal (or unordered on ARM, not on X86...)

+                case 5: FCMGTQD(v0, v1, v0); VMVNQ(v0, v0); break;   // Greater or equal or unordered

+                case 6: FCMGEQD(v0, v1, v0); VMVNQ(v0, v0); break;   // Greater or unordered

+                case 7: FCMEQQD(v0, v0, v0); 

+                        if(v0!=v1) {

+                            q0 = fpu_get_scratch(dyn); 

+                            FCMEQQD(q0, v1, v1); 

+                            VANDQ(v0, v0, q0);

+                        }

+                        break;   // not NaN

+            }

+            break;

+

         case 0xC4:

             INST_NAME("PINSRW Gx,Ed,Ib");

             nextop = F8;