[ARM64_DYNAREC] Small change on defered flag handling to make sure it's marked to None when needed

3 files changed, 67 insertions, 78 deletions

diff --git a/src/dynarec/arm64/dynarec_arm64_emit_logic.c b/src/dynarec/arm64/dynarec_arm64_emit_logic.c
index 6253eee5..e66da11c 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_logic.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_logic.c
@@ -27,7 +27,7 @@ void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3,
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_or64:d_or32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     ORRxw_REG(s1, s1, s2);
@@ -81,7 +81,7 @@ void emit_or32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int
     }
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_or64:d_or32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     ORRxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
@@ -130,7 +130,7 @@ void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_xor64:d_xor32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     EORxw_REG(s1, s1, s2);
@@ -184,7 +184,7 @@ void emit_xor32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_xor64:d_xor32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     if(!mask) {
@@ -237,7 +237,7 @@ void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_and64:d_and32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_ZF|X_SF|X_CF|X_OF) {
@@ -289,7 +289,7 @@ void emit_and32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
     IFX(X_PEND) {
         SET_DF(s4, rex.w?d_and64:d_and32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_ZF|X_SF|X_CF|X_OF) {
@@ -336,7 +336,7 @@ void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, d_or8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     ORRw_REG(s1, s1, s2);
@@ -364,7 +364,7 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4)
     }
     IFX(X_PEND) {
         SET_DF(s4, d_or8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
@@ -387,7 +387,7 @@ void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, d_xor8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     EORx_REG(s1, s1, s2);
@@ -415,7 +415,7 @@ void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
     }
     IFX(X_PEND) {
         SET_DF(s4, d_xor8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
@@ -438,7 +438,7 @@ void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, d_and8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_ZF) {
@@ -483,7 +483,7 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
     }
     IFX(X_PEND) {
         SET_DF(s4, d_and8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_ZF) {
@@ -523,7 +523,7 @@ void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, d_or16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     ORRw_REG(s1, s1, s2);
@@ -551,7 +551,7 @@ void emit_or16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s4
     }
     IFX(X_PEND) {
         SET_DF(s4, d_or16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
@@ -574,7 +574,7 @@ void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, d_xor16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     EORw_REG(s1, s1, s2);
@@ -602,7 +602,7 @@ void emit_xor16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s
     }
     IFX(X_PEND) {
         SET_DF(s4, d_xor16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
@@ -626,7 +626,7 @@ void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     MAYUSE(s2);
     IFX(X_PEND) {
         SET_DF(s4, d_and16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_ZF) {
@@ -671,7 +671,7 @@ void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s
     }
     IFX(X_PEND) {
         SET_DF(s4, d_and16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_ZF) {
diff --git a/src/dynarec/arm64/dynarec_arm64_emit_math.c b/src/dynarec/arm64/dynarec_arm64_emit_math.c
index f6b2a6ca..2050dd33 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_math.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_math.c
@@ -29,7 +29,7 @@ void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_add64:d_add32b);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF) {
@@ -98,7 +98,7 @@ void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_add64:d_add32b);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF) {
@@ -166,7 +166,7 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_sub64:d_sub32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF) {
@@ -238,7 +238,7 @@ void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         MOV64xw(s5, c);
         STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_sub64:d_sub32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF) {
@@ -309,7 +309,7 @@ void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_add8b);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF | X_OF) {
@@ -375,7 +375,7 @@ void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s4, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_add8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF | X_OF) {
@@ -418,7 +418,7 @@ void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sub8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF|X_OF|X_CF) {
@@ -465,7 +465,7 @@ void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sub8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF|X_OF|X_CF) {
@@ -512,7 +512,7 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_add16b);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF) {
@@ -645,7 +645,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sub16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_AF|X_OF|X_CF) {
@@ -988,7 +988,7 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_adc64:d_adc32b);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
@@ -1131,7 +1131,7 @@ void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_adc8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
@@ -1195,7 +1195,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_adc16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
@@ -1318,7 +1318,7 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, rex.w?d_sbb64:d_sbb32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
@@ -1467,7 +1467,7 @@ void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sbb8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
@@ -1532,7 +1532,7 @@ void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sbb16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFNATIVE_BEFORE(NF_CF) {
@@ -1654,7 +1654,7 @@ void emit_neg32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         SET_DF(s3, rex.w?d_neg64:d_neg32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -1707,7 +1707,7 @@ void emit_neg16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         SET_DF(s3, d_neg16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -1756,7 +1756,7 @@ void emit_neg8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         SET_DF(s3, d_neg8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
diff --git a/src/dynarec/arm64/dynarec_arm64_emit_shift.c b/src/dynarec/arm64/dynarec_arm64_emit_shift.c
index 058d4440..12ee8fa4 100644
--- a/src/dynarec/arm64/dynarec_arm64_emit_shift.c
+++ b/src/dynarec/arm64/dynarec_arm64_emit_shift.c
@@ -32,7 +32,7 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shl64:d_shl32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF | X_OF) {
@@ -87,7 +87,7 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shl64:d_shl32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF|X_OF) {
@@ -149,7 +149,7 @@ void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shr64:d_shr32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -202,7 +202,7 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shr64:d_shr32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -260,7 +260,7 @@ void emit_sar32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_sar64:d_sar32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -310,7 +310,7 @@ void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, i
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_sar64:d_sar32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -361,7 +361,7 @@ void emit_shl8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF | X_OF) {
@@ -401,7 +401,7 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     if(c<8) {
@@ -475,7 +475,7 @@ void emit_shr8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -512,7 +512,7 @@ void emit_shr8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -552,7 +552,7 @@ void emit_sar8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -588,7 +588,7 @@ void emit_sar8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar8);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     if(c<8) IFX(X_CF) {
@@ -634,7 +634,7 @@ void emit_shl16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF | X_OF) {
@@ -673,7 +673,7 @@ void emit_shl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shl16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     if(c<16) {
@@ -748,7 +748,7 @@ void emit_shr16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -786,7 +786,7 @@ void emit_shr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shr16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -826,7 +826,7 @@ void emit_sar16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -862,7 +862,7 @@ void emit_sar16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_sar16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -1046,9 +1046,8 @@ void emit_rcl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
 {
     MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
 
-    if (!(c%9)) return;
-
     SET_DFNONE();
+    if (!(c%9)) return;
 
     c%=9;
     BFIw(s1, xFlags, 8, 1); // insert cf
@@ -1081,9 +1080,8 @@ void emit_rcr8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s
 {
     MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
 
-    if (!(c%9)) return;
-
     SET_DFNONE();
+    if (!(c%9)) return;
 
     c%=9;
     IFX(X_OF) {
@@ -1109,9 +1107,8 @@ void emit_rcl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
 {
     MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
 
-    if (!(c%17)) return;
-
     SET_DFNONE();
+    if (!(c%17)) return;
 
     c%=17;
     BFIw(s1, xFlags, 16, 1); // insert cf
@@ -1142,9 +1139,8 @@ void emit_rcr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
 {
     MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
 
-    if (!(c%17)) return;
-
     SET_DFNONE();
+    if (!(c%17)) return;
 
     c%=17;
     BFIw(s1, xFlags, 16, 1); // insert cf
@@ -1155,7 +1151,6 @@ void emit_rcr16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int
         } else if (BOX64ENV(dynarec_test)) {
             BFCw(xFlags, F_OF, 1);
         }
-        MOVw_REG(s3, wFlags);
     }
     IFX(X_CF) {
         BFXILx(xFlags, s1, c-1, 1);
@@ -1239,15 +1234,9 @@ void emit_shrd32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, uint
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shrd64:d_shrd32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
-    if(!c) {
-        IFX(X_PEND) {
-            STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
-        }
-        return;
-    }
     IFX(X_CF) {
         BFXILxw(xFlags, s1, c-1, 1);    // set CF
     }
@@ -1298,7 +1287,7 @@ void emit_shld32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, uint
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shld64:d_shld32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -1353,7 +1342,7 @@ void emit_shrd32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
         STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
         // same flags computation as with shl64/shl32
         SET_DF(s4, rex.w?d_shrd64:d_shrd32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {
@@ -1419,7 +1408,7 @@ void emit_shld32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_shld64:d_shld32);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     MOV32w(s3, (rex.w?64:32));
@@ -1488,7 +1477,7 @@ void emit_shrd16c(dynarec_arm_t* dyn, int ninst, int s1, int s2, uint32_t c, int
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shrd16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     if(!c) {
@@ -1534,7 +1523,7 @@ void emit_shrd16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s5, int s3,
         STRH_U12(s5, xEmu, offsetof(x64emu_t, op2));
         // same flags computation as with shl64/shl32
         SET_DF(s4, d_shrd16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     ORRw_REG_LSL(s1, s1, s2, 16);   // create concat first
@@ -1577,7 +1566,7 @@ void emit_shld16c(dynarec_arm_t* dyn, int ninst, int s1, int s2, uint32_t c, int
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shld16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     if(c==0) {
@@ -1627,7 +1616,7 @@ void emit_shld16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s5, int s3,
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_shld16);
-    } else IFX(X_ALL) {
+    } else {
         SET_DFNONE();
     }
     IFX(X_CF) {