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authorptitSeb <sebastien.chev@gmail.com>2021-07-09 21:23:08 +0200
committerptitSeb <sebastien.chev@gmail.com>2021-07-09 21:23:08 +0200
commitbdb918c9c297296f6cf80634d9c15f3e5cfad253 (patch)
tree244c0d675d17a66066a111f92dea07a8cc66d3df /src
parent7ae9dca5622065b96852cf7080cd619d7ce410ad (diff)
downloadbox64-bdb918c9c297296f6cf80634d9c15f3e5cfad253.tar.gz
box64-bdb918c9c297296f6cf80634d9c15f3e5cfad253.zip
Added 66 90-97 opcodes ([DYNAREC] too) (for #44)
Diffstat (limited to 'src')
-rwxr-xr-xsrc/dynarec/dynarec_arm64_66.c19
-rw-r--r--src/emu/x64run66.c22
2 files changed, 38 insertions, 3 deletions
diff --git a/src/dynarec/dynarec_arm64_66.c b/src/dynarec/dynarec_arm64_66.c
index 15fcfaa0..0be8cfc9 100755
--- a/src/dynarec/dynarec_arm64_66.c
+++ b/src/dynarec/dynarec_arm64_66.c
@@ -454,8 +454,23 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             }

             break;

 

-        case 0x90:

-            INST_NAME("NOP");

+            case 0x90:

+            case 0x91:

+            case 0x92:

+            case 0x93:

+            case 0x94:

+            case 0x95:

+            case 0x96:

+            case 0x97:

+                gd = xRAX+(opcode&0x07)+(rex.b<<3);

+                if(gd==xRAX) {

+                    INST_NAME("NOP");

+                } else {

+                    INST_NAME("XCHG AX, Reg");

+                    MOVw_REG(x2, xRAX);

+                    BFIx(xRAX, gd, 0, 16);

+                    BFIx(gd, x2, 0, 16);

+                }

             break;

 

         case 0x98:

diff --git a/src/emu/x64run66.c b/src/emu/x64run66.c
index 1389dce4..83ccbe20 100644
--- a/src/emu/x64run66.c
+++ b/src/emu/x64run66.c
@@ -236,7 +236,27 @@ int Run66(x64emu_t *emu, rex_t rex, int rep)
             GD->word[0] = (uint16_t)(uintptr_t)ED;

         break;

 

-    case 0x90:                              /* NOP */

+        case 0x90:                      /* NOP or XCHG R8d, AX*/

+        case 0x91:

+        case 0x92:

+        case 0x93:

+        case 0x94:

+        case 0x95:

+        case 0x96:

+        case 0x97:                      /* XCHG reg,AX */

+            tmp8u = _AX+(opcode&7)+(rex.b<<3);

+            if(tmp8u!=_AX) {

+                if(rex.w) {

+                    tmp64u = R_RAX;

+                    R_RAX = emu->regs[tmp8u].q[0];

+                    emu->regs[tmp8u].q[0] = tmp64u;

+                } else {

+                    tmp16u = R_AX;

+                    R_AX = emu->regs[tmp8u].word[0];

+                    emu->regs[tmp8u].word[0] = tmp16u;

+                }

+            }

+            break;

         break;

 

     case 0x98:                               /* CBW */