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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2023-03-28 20:14:58 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-28 14:14:58 +0200 |
| commit | c0d8e7e2455987e0752643052e7c52ee4f11a1db (patch) | |
| tree | 1cf49ed05250017b9dc6183488a11255a5ccd981 /src | |
| parent | d73ff21b27b7f2fdca3f817fb37faefe388439d8 (diff) | |
| download | box64-c0d8e7e2455987e0752643052e7c52ee4f11a1db.tar.gz box64-c0d8e7e2455987e0752643052e7c52ee4f11a1db.zip | |
[RV64_DYNAREC] Fixed issues caught by newly added cosim framework (#645)
* [RV64_DYNAREC] Fixed an issue in 0F AF IMUL opcode * [RV64_DYNAREC] Fixed typos with LUI * [RV64_DYNAREC] Fixed 66 D1,D3 /7 SAR opcode * [RV64_DYNAREC] Fixed 66 69,6B IMUL opcode
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_0f.c | 3 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_66.c | 10 |
2 files changed, 9 insertions, 4 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_0f.c b/src/dynarec/rv64/dynarec_rv64_0f.c index 965f4fea..038be66b 100644 --- a/src/dynarec/rv64/dynarec_rv64_0f.c +++ b/src/dynarec/rv64/dynarec_rv64_0f.c @@ -400,7 +400,8 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni SRLI(x3, gd, 32); UFLAG_OP1(x3); UFLAG_DF(x3, d_imul32); - SEXT_W(gd, gd); + SLLI(gd, gd, 32); + SRLI(gd, gd, 32); } else { MULxw(gd, gd, ed); } diff --git a/src/dynarec/rv64/dynarec_rv64_66.c b/src/dynarec/rv64/dynarec_rv64_66.c index 74fdd47d..547ae7f2 100644 --- a/src/dynarec/rv64/dynarec_rv64_66.c +++ b/src/dynarec/rv64/dynarec_rv64_66.c @@ -117,7 +117,7 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni SRLI(x1, x1, 48); MOV32w(x2, i32); emit_or16(dyn, ninst, x1, x2, x3, x4); - LUI(x3, 0xfff0); + LUI(x3, 0xffff0); AND(xRAX, xRAX, x3); OR(xRAX, xRAX, x1); break; @@ -150,7 +150,7 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni SRLI(x1, x1, 48); MOV32w(x2, i32); emit_and16(dyn, ninst, x1, x2, x3, x4); - LUI(x3, 0xfff0); + LUI(x3, 0xffff0); AND(xRAX, xRAX, x3); OR(xRAX, xRAX, x1); break; @@ -248,6 +248,8 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni if(opcode==0x69) i32 = F16S; else i32 = F8S; MOV32w(x2, i32); MULW(x2, x2, x1); + SLLI(x2, x2, 48); + SRLI(x2, x2, 48); UFLAG_RES(x2); gd=x2; GWBACK; @@ -376,7 +378,7 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni INST_NAME("NOP"); } else { INST_NAME("XCHG AX, Reg"); - LUI(x4, 0xfff0); + LUI(x4, 0xffff0); // x2 <- rax MV(x2, xRAX); // rax[15:0] <- gd[15:0] @@ -579,6 +581,8 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni GETSEW(x1, 0); UFLAG_OP12(ed, x4) SRA(ed, ed, x4); + SLLI(ed, ed, 48); + SRLI(ed, ed, 48); EWBACK; UFLAG_RES(ed); UFLAG_DF(x3, d_sar16); |