[DYNAREC] Added 8B opcode

4 files changed, 40 insertions, 2 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index 52b58dfc..60c12748 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -248,7 +248,6 @@
 #define ORNw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
 #define ORNxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
 #define MOVx(Rd, Rm)                    ORRx_REG(Rd, xZR, Rm)
-#define MOVx_LSL(Rm, Rd, lsl)           ORRx_REG_LSL(Rd, xZR, Rm, lsl)
 #define MOVw(Rd, Rm)                    ORRw_REG(Rd, xZR, Rm)
 #define MOVxw(Rd, Rm)                   ORRxw_REG(Rd, xZR, Rm)
 #define MVNx(Rd, Rm)                    ORNx_REG(Rd, xZR, Rm)
@@ -282,6 +281,9 @@
 
 // UBFX
 #define UBFM_gen(sf, N, immr, imms, Rn, Rd)    ((sf)<<31 | 0b10<<29 | 0b100110<<23 | (N)<<22 | (immr)<<16 | (imms)<<10 | (Rn)<<5 | (Rd))
+#define UBFMx(Rd, Rn, immr, imms)       EMIT(UBFM_gen(1, 1, immr, imms, Rn, Rd))
+#define UBFMw(Rd, Rn, immr, imms)       EMIT(UBFM_gen(0, 0, immr, imms, Rn, Rd))
+#define UBFMxw(Rd, Rn, immr, imms)      EMIT(UBFM_gen(rex.w, rex.w, immr, imms, Rn, Rd))
 #define UBFXx(Rd, Rn, lsb, width)       EMIT(UBFM_gen(1, 1, (lsb), (lsb)+(width)-1, Rn, Rd))
 #define UBFXw(Rd, Rn, lsb, width)       EMIT(UBFM_gen(0, 1, (lsb), (lsb)+(width)-1, Rn, Rd))
 #define UXTBx(Rd, Rn)                   EMIT(UBFM_gen(1, 1, 0, 7, Rn, Rd))
@@ -291,6 +293,8 @@
 #define LSRx(Rd, Rn, shift)             EMIT(UBFM_gen(1, 1, shift, 63, Rn, Rd))
 #define LSRw(Rd, Rn, shift)             EMIT(UBFM_gen(0, 0, shift, 31, Rn, Rd))
 #define LSRxw(Rd, Rn, shift)            EMIT(UBFM_gen(rex.w, rex.w, shift, (rex.w)?63:31, Rn, Rd))
+#define LSLx(Rd, Rn, lsl)               UBFMx(Rd, Rn, ((-(lsl))%64)&63, 63-(lsl))
+#define LSLw(Rd, Rn, lsl)               UBFMw(Rd, Rn, ((-(lsl))%32)&31, 31-(lsl))
 
 // LSRV
 #define LSRV_gen(sf, Rm, op2, Rn, Rd)   ((sf)<<31 | 0b11010110<<21 | (Rm)<<16 | 0b0010<<12 | (op2)<<10 | (Rn)<<5 | (Rd))
diff --git a/src/dynarec/arm64_printer.c b/src/dynarec/arm64_printer.c
index dcfa3032..56dfd5c3 100755
--- a/src/dynarec/arm64_printer.c
+++ b/src/dynarec/arm64_printer.c
@@ -81,6 +81,8 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
     #define shift a.h

     #define hw a.w

     #define cond a.c

+    #define immr a.r

+    #define imms a.s

     // --- LDR / STR

     if(isMask(opcode, "1x111000010iiiiiiiii01nnnnnttttt", &a)) {

         int size = (opcode>>30)&3;

@@ -257,6 +259,26 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
     }

     // ---- LOGIC

 

+    // ---- SHIFT

+    if(isMask(opcode, "f10100110Nrrrrrrssssssnnnnnddddd", &a)) {

+        if(sf && imms!=0b111111 && imms+1==immr)

+            snprintf(buff, sizeof(buff), "LSL %s, %s, %d", Xt[Rd], Xt[Rn], 63-imms);

+        else if(!sf && imms!=0b011111 && imms+1==immr)

+            snprintf(buff, sizeof(buff), "LSL %s, %s, %d", Wt[Rd], Wt[Rn], 31-imms);

+        else if(sf && imms==0b111111)

+            snprintf(buff, sizeof(buff), "LSR %s, %s, %d", Xt[Rd], Xt[Rn], immr);

+        else if(!sf && imms==0b011111)

+            snprintf(buff, sizeof(buff), "LSR %s, %s, %d", Wt[Rd], Wt[Rn], immr);

+        else if(immr==0 && imms==0b000111)

+            snprintf(buff, sizeof(buff), "UXTB %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn]);

+        else if(immr==0 && imms==0b001111)

+            snprintf(buff, sizeof(buff), "UXTH %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn]);

+        else

+            snprintf(buff, sizeof(buff), "UBFM %s, %s, %d, %d", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], immr, imms);

+

+        return buff;

+    }

+

     // ---- BRANCH / TEST

     if(isMask(opcode, "1101011000011111000000nnnnn00000", &a)) {

         snprintf(buff, sizeof(buff), "BR %s", Xt[Rn]);

diff --git a/src/dynarec/dynarec_arm64_00.c b/src/dynarec/dynarec_arm64_00.c
index 90ce3874..26040089 100755
--- a/src/dynarec/dynarec_arm64_00.c
+++ b/src/dynarec/dynarec_arm64_00.c
@@ -148,6 +148,18 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             }
             break;
 
+        case 0x8B:
+            INST_NAME("MOV Gd, Ed");
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg
+                MOVxw(gd, xRAX+(nextop&7)+(rex.b<<3));
+            } else {                    // mem <= reg
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, 0, 0);
+                LDRxw_U12(gd, ed, fixedaddress);
+            }
+            break;
+
         case 0x8D:
             INST_NAME("LEA Gd, Ed");
             nextop=F8;
diff --git a/src/dynarec/dynarec_arm64_helper.c b/src/dynarec/dynarec_arm64_helper.c
index 2ddb3e99..014bca70 100755
--- a/src/dynarec/dynarec_arm64_helper.c
+++ b/src/dynarec/dynarec_arm64_helper.c
@@ -47,7 +47,7 @@ uintptr_t geted(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, u
                         MOV64x(scratch, tmp);
                         ADDx_REG_LSL(ret, scratch, xRAX+sib_reg+(rex.x<<3), (sib>>6));
                     } else {
-                        MOVx_LSL(ret, xRAX+sib_reg+(rex.x<<3), (sib>>6));
+                        LSLx(ret, xRAX+sib_reg+(rex.x<<3), (sib>>6));
                         *fixaddress = tmp;
                     }
                 } else {