[DYNAREC] Added F2 0F 2A opcode

4 files changed, 32 insertions, 14 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index d69e3a71..b90b0bc4 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -936,23 +936,23 @@
 #define FCVT_D_S(Dd, Sn)            EMIT(FCVT_precision(0b00, 0b01, Sn, Dd))
 #define FCVT_S_D(Sd, Dn)            EMIT(FCVT_precision(0b01, 0b00, Dn, Sd))
 
-#define FCVTXN_gen(Q, sz, Rn, Rd)   ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10110<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define FCVTXN_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10110<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 // Convert Vn from 2*Double to lower Vd as 2*float and clears the upper half
-#define FCVTXN(Vd, Vn)              EMIT(FCVTXN_gen(0, 1, Vn, Vd))
+#define FCVTXN(Vd, Vn)              EMIT(FCVTXN_vector(0, 1, Vn, Vd))
 // Convert Vn from 2*Double to higher Vd as 2*float
-#define FCVTXN2(Vd, Vn)             EMIT(FCVTXN_gen(1, 1, Vn, Vd))
+#define FCVTXN2(Vd, Vn)             EMIT(FCVTXN_vector(1, 1, Vn, Vd))
 
-#define FCVTL_gen(Q, sz, Rn, Rd)    ((Q)<<30 | 0<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10111<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define FCVTL_vector(Q, sz, Rn, Rd)     ((Q)<<30 | 0<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10111<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 // Convert lower Vn from 2*float to Vd as 2*double
-#define FCVTL(Vd, Vn)               EMIT(FCVTL_gen(0, 1, Vn, Vd))
+#define FCVTL(Vd, Vn)               EMIT(FCVTL_vector(0, 1, Vn, Vd))
 // Convert higher Vn from 2*float to Vd as 2*double
-#define FCVTL2(Vd, Vn)              EMIT(FCVTL_gen(1, 1, Vn, Vd))
+#define FCVTL2(Vd, Vn)              EMIT(FCVTL_vector(1, 1, Vn, Vd))
 
 #define SCVTF_scalar(sf, type, rmode, opcode, Rn, Rd)   ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (rmode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
-#define SCVTSw(Sd, Wn)              EMIT(SCVTF_scalar(0, 0b00, 0b00, 0b010, Wn, Sd))
-#define SCVTDw(Dd, Wn)              EMIT(SCVTF_scalar(0, 0b00, 0b01, 0b010, Wn, Dd))
-#define SCVTSx(Sd, Xn)              EMIT(SCVTF_scalar(1, 0b00, 0b00, 0b010, Xn, Sd))
-#define SCVTDx(Dd, Xn)              EMIT(SCVTF_scalar(1, 0b00, 0b01, 0b010, Xn, Dd))
+#define SCVTFSw(Sd, Wn)             EMIT(SCVTF_scalar(0, 0b00, 0b00, 0b010, Wn, Sd))
+#define SCVTFDw(Dd, Wn)             EMIT(SCVTF_scalar(0, 0b01, 0b00, 0b010, Wn, Dd))
+#define SCVTFSx(Sd, Xn)             EMIT(SCVTF_scalar(1, 0b00, 0b00, 0b010, Xn, Sd))
+#define SCVTFDx(Dd, Xn)             EMIT(SCVTF_scalar(1, 0b01, 0b00, 0b010, Xn, Dd))
 
 #define SCVTF_vector_scalar(U, sz, Rn, Rd)    (1<<30 | (U)<<29 | 0b11110<<24 | (sz)<<22 | 0b10000<<17 | 0b11101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 #define SCVTFSS(Vd, Vn)             EMIT(SCVT_vector_scalar(0, 0, Vn, Vd))
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index 55df44a6..c4899402 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -38,6 +38,10 @@
     gd = ((nextop&0x38)>>3)+(rex.r<<3); \

     a = sse_get_reg(dyn, ninst, x1, gd)

 

+#define GETGX_empty(a)                  \

+    gd = ((nextop&0x38)>>3)+(rex.r<<3); \

+    a = sse_get_reg_empty(dyn, ninst, x1, gd)

+

 uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)

 {

     uint8_t opcode = F8;

@@ -594,8 +598,8 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xEF:

             INST_NAME("PXOR Gx,Ex");

             nextop = F8;

-            gd = ((nextop&0x38)>>3)+(rex.r<<3);

-            if(nextop+(rex.b<<3)==0xC0+gd) {

+            GETG;

+            if(MODREG && ((nextop&7)+(rex.b<<3)==gd)) {

                 // special case for PXOR Gx, Gx

                 q0 = sse_get_reg_empty(dyn, ninst, x1, gd);

                 VEORQ(q0, q0, q0);

diff --git a/src/dynarec/dynarec_arm64_f20f.c b/src/dynarec/dynarec_arm64_f20f.c
index 95bca08a..fdad0db7 100755
--- a/src/dynarec/dynarec_arm64_f20f.c
+++ b/src/dynarec/dynarec_arm64_f20f.c
@@ -90,6 +90,20 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             }

             break;

 

+        case 0x2A:

+            INST_NAME("CVTSI2SD Gx, Ed");

+            nextop = F8;

+            GETGX(v0);

+            GETED(0);

+            d1 = fpu_get_scratch(dyn);

+            if(rex.w) {

+                SCVTFDx(d1, ed);

+            } else {

+                SCVTFDw(d1, ed);

+            }

+            VMOVeD(v0, 0, d1, 0);

+            break;

+

         case 0x51:

             INST_NAME("SQRTSD Gx, Ex");

             nextop = F8;

diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c
index e732d3e0..db2b8619 100755
--- a/src/dynarec/dynarec_arm64_f30f.c
+++ b/src/dynarec/dynarec_arm64_f30f.c
@@ -95,9 +95,9 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             GETED(0);

             d1 = fpu_get_scratch(dyn);

             if(rex.w) {

-                SCVTSx(d1, ed);

+                SCVTFSx(d1, ed);

             } else {

-                SCVTSw(d1, ed);

+                SCVTFSw(d1, ed);

             }

             VMOVeS(v0, 0, d1, 0);

             break;