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| author | ptitSeb <sebastien.chev@gmail.com> | 2025-04-30 15:58:09 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2025-04-30 15:58:09 +0200 |
| commit | c835227b8bd0516577d5d8373a1a7340dd385537 (patch) | |
| tree | 98c82146ee33dae7a40543b60a14fc84ebb8922a /src | |
| parent | 57f07446eab75538f5a100d763ce0f73834c96a0 (diff) | |
| download | box64-c835227b8bd0516577d5d8373a1a7340dd385537.tar.gz box64-c835227b8bd0516577d5d8373a1a7340dd385537.zip | |
[ARM64_DYNAREC] Fixed a potential issue with (V)STMXCSR opcodes
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_0f.c | 2 | ||||
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_avx_0f.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index 9b890f63..a4cf07ec 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -1976,6 +1976,7 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin INST_NAME("STMXCSR Md"); addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0); LDRw_U12(x4, xEmu, offsetof(x64emu_t, mxcsr)); + STW(x4, ed, fixedaddress); if(BOX64ENV(sse_flushto0)) { // sync with fpsr, with mask from mxcsr MRS_fpsr(x1); @@ -1987,7 +1988,6 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin //BFXILw(x3, x4, 7, 6); // this would the mask, but let's ignore that for now BFIw(x4, x1, 0, 6); // inject back the flags } - STW(x4, ed, fixedaddress); break; case 4: INST_NAME("XSAVE Ed"); diff --git a/src/dynarec/arm64/dynarec_arm64_avx_0f.c b/src/dynarec/arm64/dynarec_arm64_avx_0f.c index 9dda9b02..00ecd917 100644 --- a/src/dynarec/arm64/dynarec_arm64_avx_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_avx_0f.c @@ -684,6 +684,7 @@ uintptr_t dynarec64_AVX_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int INST_NAME("VSTMXCSR Md"); addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0); LDRw_U12(x4, xEmu, offsetof(x64emu_t, mxcsr)); + STW(x4, ed, fixedaddress); if(BOX64ENV(sse_flushto0)) { // sync with fpsr, with mask from mxcsr MRS_fpsr(x1); @@ -695,7 +696,6 @@ uintptr_t dynarec64_AVX_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int //BFXILw(x3, x4, 7, 6); // this would the mask, but let's ignore that for now BFIw(x4, x1, 0, 6); // inject back the flags } - STW(x4, ed, fixedaddress); break; default: DEFAULT; |