[ARM64_DYNAREC] Added 66 0F 3A 40 opcode (with tests)

3 files changed, 42 insertions, 0 deletions

diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h
index 4a939eb8..79e24f02 100644
--- a/src/dynarec/arm64/arm64_emitter.h
+++ b/src/dynarec/arm64/arm64_emitter.h
@@ -1104,6 +1104,12 @@
 #define FADDP_vector(Q, sz, Rm, Rn, Rd) ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11010<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VFADDPQS(Vd, Vn, Vm)        EMIT(FADDP_vector(1, 0, Vm, Vn, Vd))
 #define VFADDPQD(Vd, Vn, Vm)        EMIT(FADDP_vector(1, 1, Vm, Vn, Vd))
+#define VFADDPS(Vd, Vn, Vm)         EMIT(FADDP_vector(0, 0, Vm, Vn, Vd))
+#define VFADDPD(Vd, Vn, Vm)         EMIT(FADDP_vector(0, 1, Vm, Vn, Vd))
+
+#define FADDP_scalar(sz, Rn, Rd)        (0b01<<30 | 1<<29 | 0b11110<<24 | (sz)<<22 | 0b11000<<17 | 0b01101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define FADDPS(Sd, Sn)              EMIT(FADDP_scalar(0, Sn, Sd))
+#define FADDPD(Dd, Dn)              EMIT(FADDP_scalar(1, Dn, Dd))
 
 // NEG / ABS
 #define FNEGABS_scalar(type, opc, Rn, Rd)  (0b11110<<24 | (type)<<22 | 1<<21 | (opc)<<15 | 0b10000<<10 | (Rn)<<5 | (Rd))
diff --git a/src/dynarec/arm64/arm64_printer.c b/src/dynarec/arm64/arm64_printer.c
index 70f96d34..f8d09c89 100644
--- a/src/dynarec/arm64/arm64_printer.c
+++ b/src/dynarec/arm64/arm64_printer.c
@@ -1145,6 +1145,20 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         return buff;

     }

 

+    // FADDP

+    if(isMask(opcode, "0Q1011100f1mmmmm110101nnnnnddddd", &a)) {

+        char s = a.Q?'V':'D';

+        char d = sf?'D':'S';

+        int n = (a.Q && !sf)?4:2;

+        snprintf(buff, sizeof(buff), "VFADDP %c%d.%d%c, %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d, s, Rm, n, d);

+        return buff;

+    }

+    if(isMask(opcode, "011111100f110000110110nnnnnddddd", &a)) {

+        char s = (sf==0)?'S':((sf==1)?'D':'?');

+        snprintf(buff, sizeof(buff), "FADDP %c%d, %c%d, %c%d", s, Rd, s, Rn, s, Rm);

+        return buff;

+    }

+

     // SQRT

     if(isMask(opcode, "0Q1011101f100001111110nnnnnddddd", &a)) {

         char s = a.Q?'V':'D';

diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index f5e689e1..101b05dd 100644
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -1195,6 +1195,28 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                     }

                     break;

 

+                case 0x40:

+                    INST_NAME("DPPS Gx, Ex, Ib");

+                    nextop = F8;

+                    GETGX(q0, 1);

+                    GETEX(q1, 0, 1);

+                    u8 = F8;

+                    v0 = fpu_get_scratch(dyn);

+                    VFMULQS(v0, q0, q1);

+                    // mask some, duplicate all, mask some

+                    for(int i=0; i<4; ++i)

+                        if(!(u8&(1<<(4+i)))) {

+                            VMOVQSfrom(v0, i, xZR);

+                        }

+                    VFADDPQS(v0, v0, v0);

+                    FADDPS(v0, v0);

+                    VDUPQ_32(q0, v0, 0);

+                    for(int i=0; i<4; ++i)

+                        if(!(u8&(1<<i))) {

+                            VMOVQSfrom(q0, i, xZR);

+                        }

+                    break;

+

                 case 0x44:

                     INST_NAME("PCLMULQDQ Gx, Ex, Ib");

                     nextop = F8;