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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-17 10:17:50 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-17 10:17:50 +0100 |
| commit | d1a037b38b647ac54c11a1b1e00a800205193ada (patch) | |
| tree | 8d643f6dd29fb3161cdb46ebe2d687b39f8fa8c6 /src | |
| parent | a552e5a48f92004a1a76778bece8bf12a1a62ef2 (diff) | |
| download | box64-d1a037b38b647ac54c11a1b1e00a800205193ada.tar.gz box64-d1a037b38b647ac54c11a1b1e00a800205193ada.zip | |
[DYNAREC] Small optim for MOV64x on negative values
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/arm64_emitter.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h index f3750b07..98f339e9 100755 --- a/src/dynarec/arm64_emitter.h +++ b/src/dynarec/arm64_emitter.h @@ -108,12 +108,17 @@ #define MOVKw_LSL(Rd, imm16, shift) EMIT(MOVK_gen(0, (shift)/16, (imm16)&0xffff, Rd)) #define MOV32w(Rd, imm32) {MOVZw(Rd, (imm32)&0xffff); if((imm32)&0xffff0000) {MOVKw_LSL(Rd, ((imm32)>>16)&0xffff, 16);}} -#define MOV64x(Rd, imm64) { \ - MOVZx(Rd, ((uint64_t)(imm64))&0xffff); \ - if(((uint64_t)(imm64))&0xffff0000) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>16)&0xffff, 16);} \ - if(((uint64_t)(imm64))&0xffff00000000L) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>32)&0xffff, 32);} \ - if(((uint64_t)(imm64))&0xffff000000000000L) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>48)&0xffff, 48);}\ -} +#define MOV64x(Rd, imm64) \ + if(~((uint64_t)(imm64))<0xffff) { \ + MOVZx(Rd, (~(uint64_t)(imm64))&0xffff); \ + MVNx(Rd, Rd); \ + } else { \ + MOVZx(Rd, ((uint64_t)(imm64))&0xffff); \ + if(((uint64_t)(imm64))&0xffff0000) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>16)&0xffff, 16);} \ + if(((uint64_t)(imm64))&0xffff00000000L) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>32)&0xffff, 32);} \ + if(((uint64_t)(imm64))&0xffff000000000000L) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>48)&0xffff, 48);} \ + } + // ADD / SUB #define ADDSUB_REG_gen(sf, op, S, shift, Rm, imm6, Rn, Rd) ((sf)<<31 | (op)<<30 | (S)<<29 | 0b01011<<24 | (shift)<<22 | (Rm)<<16 | (imm6)<<10 | (Rn)<<5 | (Rd)) |